FOR i:
INT
DECREASING IN [0..Cluster2.historySize-1)
DO
ia: REF IFU2.IFUState ← NARROW[states[i+1].data[ifu]];
ib: REF IFU2.IFUState ← NARROW[states[i].data[ifu]];
ea: EU2.EU2State ← NARROW[states[i+1].data[eu]];
eb: EU2.EU2State ← NARROW[states[i].data[eu]];
xbus: IFU2.RegAddrRec ← LOOPHOLE[ib.XBus];
IF states[i].phase=a THEN LOOP;
IF states[i+1].phase#a THEN ERROR;
IF states[i].phase#b THEN ERROR;
IF states[i].cycle#states[i+1].cycle THEN ERROR;
tos.PutF["%3g ", IO.int[states[i].cycle] ];
Current
CondRope[ "Rdy ", ia.InstReadyAB ];
tos.PutF["%6g ", IO.rope[ OpCodeRp[ ia.OpAB ] ] ];
tos.PutF["%g ", IO.rope[ NextMacroRp[ ib.NextMacroBA ] ] ];
CondRope[ "Rd0 ", ib.DPCmndIsRd0BA ];
CondRope[ "Rd2 ", ib.DPCmndIsRd2BA ];
CondRope[ "ILock ", ib.Stage1BHoldBA ];
tos.PutF["X:%02x ", IO.int[ xbus.aAddr ] ];
tos.PutF["%02x ", IO.int[ xbus.bAddr ] ];
tos.PutF["%02x ", IO.int[ xbus.cAddr ] ];
tos.PutF["l:%g ", IO.rope[ LtSrcRp[ xbus.aluLeftSrc ] ] ];
tos.PutF["r:%g ", IO.rope[ RtSrcRp[ xbus.aluRightSrc ] ] ];
tos.PutF["s:%g ", IO.rope[ StSrcRp[ xbus.storeSrc ] ] ];
CondRope[ "S3C", xbus.st3AisC ];
tos.PutF["%4g ", IO.rope[ AluOpRp[ ib.ctlPipe2AB.aluOp ] ] ];
tos.PutF["2:%g ", IO.rope[ CondSelectRp[ ib.ctlPipe2AB.condSel ] ] ];
CondRope[ "Cnd ", ib.EUCondition2BA ];
tos.PutF["3:%g ", IO.rope[ CondSelectRp[ ib.ctlPipe3AB.condSel ] ] ];
CondRope[ "Rd", ib.ctlPipe3AB.rdFromPBus ];
CondRope[ "Wt", ib.ctlPipe3AB.writeToPBus ];
tos.PutF["%8x", IO.card[ ea.simRegs[EU2Utils.left]]];
tos.PutF["%8x", IO.card[ ea.simRegs[EU2Utils.right]]];
tos.PutF["%8x", IO.card[ eb.simRegs[EU2Utils.r2B]]];
EU Communication
tos.PutF["Xus1B:%02x ", IO.int[ xbus.aAddr ] ];
tos.PutF["%02x ", IO.int[ xbus.bAddr ] ];
tos.PutF["%02x ", IO.int[ xbus.cAddr ] ];
tos.PutF["l:%g ", IO.rope[ LtSrcRp[ xbus.aluLeftSrc ] ] ];
tos.PutF["r:%g ", IO.rope[ RtSrcRp[ xbus.aluRightSrc ] ] ];
tos.PutF["s:%g ", IO.rope[ StSrcRp[ xbus.storeSrc ] ] ];
CondRope[ "S3C", xbus.st3AisC ];
tos.PutF["%4g ", IO.rope[ AluOpRp[ ib.ctlPipe2AB.aluOp ] ] ];
tos.PutF["2:%g ", IO.rope[ CondSelectRp[ ib.ctlPipe2AB.condSel ] ] ];
CondRope[ "Cnd ", ib.EUCondition2BA ];
tos.PutF["3:%g ", IO.rope[ CondSelectRp[ ib.ctlPipe3AB.condSel ] ] ];
CondRope[ "Rd", ib.ctlPipe3AB.rdFromPBus ];
CondRope[ "Wt", ib.ctlPipe3AB.writeToPBus ];
EU State
tos.PutF["2A:%8x ", IO.card[ ea.simRegs[EU2Utils.left]]];
tos.PutF["2A:%8x ", IO.card[ ea.simRegs[EU2Utils.right]]];
tos.PutF["2B:%8x ", IO.card[ eb.simRegs[EU2Utils.r2B]]];
Instruction
CondRope[ "Rdy ", ia.InstReadyAB ];
tos.PutF["%6g ", IO.rope[ OpCodeRp[ ia.OpAB ] ] ];
tos.PutF["%g ", IO.rope[ NextMacroRp[ ib.NextMacroBA ] ] ];
CondRope[ "Rd0BA ", ib.DPCmndIsRd0BA ];
CondRope[ "Rd2BA ", ib.DPCmndIsRd2BA ];
CondRope[ "ILock ", ib.Stage1BHoldBA ];
Pipe controls
CondRope[ "Ld1A ", ia.LoadStage1Ac ];
CondRope[ "Ld1B ", NOT ia.NotBcLoadStage1AB ];
CondRope[ "Ld2A ", ia.LoadStage2Ac ];
CondRope[ "(bub) ", ia.Stage2ABubbleBA ];
CondRope[ "Abrt2B ", ib.Stage2BAbortAB ];
CondRope[ "Ld3A ", ia.LoadStage3Ac ];
CondRope[ "(abrt) ", ia.Stage3AAbortBA ];
CJump
tos.PutF["CE2:%6g ", IO.rope[ CondEffectRp[ ia.CondEffect2AB ] ] ];
tos.PutF["CS2:%3g ", IO.rope[ CondSelectRp[ ia.ctlPipe2AB.condSel ] ] ];
CondRope[ "Cond ", ia.EUCondition2BA ];
FetcherControl
CondRope[ "Ftch ", ia.NewFetchBA ];
tos.PutF["a:%08x ", IO.card[ ia.fetchAddrBA ] ];
tos.PutF["d:%08x ", IO.card[ ib.IPDataBA ] ];
CondRope[ "Rjt ", ib.IPRejectBA ];
CondRope[ "Ftchng ", ia.FetchingAB ];
tos.PutF["%x ", IO.card[ ib.wtAB ] ];
tos.PutF["%x ", IO.card[ ib.rdAB ] ];
CondRope[ "IRdy ", ia.InstReadyAB ];
tos.PutF["%g ", IO.rope[ NextMacroRp[ ib.NextMacroBA ] ] ];
TerminalIO.WriteLn[] ENDLOOP;