CurrentIFUVersion: Dragon.HexByte = 1;
Byte: TYPE = [0..256);
QPh: TYPE = {A, ab, B, ba};
II:
TYPE = {
KBus, EUAluOp2AB, EUCondSel2AB, EUCondition2B, EURdFromPBus3AB, EUWriteToPBus3AB,
UserMode2BA,
DPCmdA, DPRejectB, DPFaultB,
IPData, IPCmdFetchA, IPRejectB, IPFaultingB,
DShA, DShB, DShRd, DShWt, DShIn, DShOut,
ResetAB, RescheduleAB, PhA, PhB, NotPhA, NotPhB,
Vdd, Gnd, PadVdd, PadGnd };
MicroInstDisposition: TYPE = {unready, valid, interlocked, killed2b, killed3a, killed3b};
LogPipeState:
TYPE =
RECORD [
pc: Dragon.HexWord,
op: DragOpsCross.Inst ← x374b,
alpha, beta, gamma, delta: Dragon.HexByte ← 0,
microCyc: NAT ← 0,
disposition: MicroInstDisposition ← unready ];
RegAddrRec:
TYPE =
MACHINE
DEPENDENT
RECORD [
.. this will be LOOPHOLE'd to LONG CARDINAL, so its low-order word must appear first, as does that of a LONG CARDINAL (sigh!)
cAddr (0: 0..7): Dragon.HexByte,
st3AisC (0: 8..8): BOOL,
aluLeftSrc (0: 9..10): Dragon.ALULeftSources,
aluRightSrc (0: 11..13): Dragon.ALURightSources,
storeSrc (0: 14..15): Dragon.Store2ASources,
aAddr (1: 0..7): Dragon.HexByte,
bAddr (1: 8..15): Dragon.HexByte ];
BitSeq:
TYPE =
RECORD [
-- for debugging shift register
size: [0..1024] ← 1024,
bits: PACKED ARRAY [0..1024) OF BOOL ];
BasicInst:
TYPE =
RECORD [
cycle: INT,
instr: INT,
trapped: BOOL, -- this instruction was aborted
trapPC: Dragon.HexWord, -- if aborted, then why?
pc: Dragon.HexWord,
op: DragOpsCross.Inst,
alpha, beta, gamma, delta: Dragon.HexByte ];
GetLogProc: TYPE = PROC [ data: REF ANY ] RETURNS [ s: Core.STREAM ];
GetCycleProc: TYPE = PROC [ data: REF ANY ] RETURNS [ cycle: INT ];
CheckSynchProc: TYPE = PROC [ data: REF ANY, basicInst: BasicInst ] RETURNS [ deltaInstrCount: INT ← 1 ];
IFUTypeData:
TYPE =
RECORD [
data: REF ANY,
getLog: GetLogProc ← NIL,
getCycle: GetCycleProc ← NIL,
checkSynch: CheckSynchProc ← NIL ];
IFUState: TYPE = REF IFUStateRec;
IFUStateRec:
TYPE =
RECORD [
data: REF IFUTypeData,
public: Core.Wire,
oldP: Ports.Port,
maxConvergPasses: NAT,
oldState: IFUState,
initialized: BOOL ← FALSE, -- used to prevent signals before one pass of both phases
ph: QPh ← A, -- for simulation only, not represented in hardware
XBus: Dragon.HexWord, -- main data bus within IFU, sometimes connects to KBus
PCBusB: Dragon.HexWord,
IFUSrcComplete.LtDrPadIO
ResetAB: BOOL, -- actually from pad, doesn't belong here
ResetBA: BOOL,
RescheduleBA: BOOL,
IPRejectBA: BOOL,
IPFaultingBA: BOOL,
X2ASrcLit2Ac: BOOL,
KPadsOut3BA: BOOL, -- xxx not yet matched in ifu2impl
KPadsIn4Ac: BOOL, -- xxx not yet matched in ifu2impl
IFUSrcComplete.RtDrPadIO
DPRejectBA: BOOL,
DPFaultBA: Dragon.PBusFaults,
DPFaultAB: Dragon.PBusFaults,
EUCondition2BA: BOOL,
IFUSrcFetchControler.FetchIndexing
Outputs
FetchWtAB: [0..4),
FetchRdBA: [0..16),
FetchBytesM1AB: [0..32),
Internal State
wtBA: [0..32),
rdAB: [0..32),
wtAB: [0..32),
rdBA: [0..32),
Fetch
fetchAddrBA: Dragon.HexWord,
fetchAddrAB: Dragon.HexWord,
FetchBuf
iBuf: ARRAY [0..16) OF Dragon.HexByte,
OpAB: Dragon.HexByte,
AlphaAB: Dragon.HexByte,
BetaAB: Dragon.HexByte,
GammaAB: Dragon.HexByte,
DeltaAB: Dragon.HexByte,
IFUPLAFetchDecode.FetchRdDecodeIn B Input
IFUPLAFetchDecode.FetchRdDecodeOut
Ac Output
FetchBufRdByteAc: PACKED ARRAY [0..16) OF BOOL,
IFUPLAFetchDecode.FetchWtDecodeIn A Input
IFUPLAFetchDecode.FetchWtDecodeOut
Bc Output
FetchBufWtWdBc: PACKED ARRAY [0..4) OF BOOL,
IFUPLAFetchControl.FetchControlIn B Input
IFUPLAFetchControl.FetchControlOut
B Output
NewFetchBA: BOOL,
FetchWtIndexCtlBA: IFUPLAFetchControl.FetchWtIndexCtl,
OpLengthbBA: [0..8),
InstFault0BA: BOOL,
A Output
JumpPendingAB: BOOL,
FetchingAB: BOOL,
FetchingBA: BOOL,
IPFaultedAB: BOOL,
NotInstReadyAB: BOOL,
JumpOffsetAB: IFUPLAFetchControl.JumpOffsetSel,
OpLengthAB: [0..8),
Aux signals
InstReadyAB: BOOL,
IPData: Dragon.HexWord,
IFUPLAStackControl.StackDecodeIn B Input
IFUPLAStackControl.StackDecodeWtPOut
StkLdPAc: PACKED ARRAY [0..16) OF BOOL,
IFUPLAStackControl.StackDecodeWtLOut
StkLdLAc: PACKED ARRAY [0..16) OF BOOL,
IFUPLAStackControl.StackDecodeRdOut
StkRdAc: PACKED ARRAY [0..16) OF BOOL,
IFUPLAStackControl.StackAControlIn B Input
IFUPLAStackControl.StackAControlOut
A Output
StackAdjTosAB: BOOL,
StackAddendIsOnesAB: BOOL,
StackCarryIsOneAB: BOOL,
IFUPLAStackControl.StackBControlIn B Input
IFUPLAStackControl.StackBControlOut
B Output
Push3BA: BOOL,
Pop3BA: BOOL,
IStkNearlyFullBA: BOOL,
IFUSrcStackControler.StackIndexing
TosAB: [0..32),
TosBA: [0..32),
BosAB: [0..32),
BosBA: [0..32),
StackDiffBA: [0..32),
IFUPLAInterlock.InterlockIn B Input
IFUPLAInterlock.InterlockOut
B Output
Stage1BHoldBA: BOOL,
EUAluLeftSrc1B: Dragon.ALULeftSources,
EUAluRightSrc1B: Dragon.ALURightSources,
EUStore2ASrc1B: Dragon.Store2ASources,
EUSt3AIsCBus1BA: BOOL,
IFUPLAMainPipeControl.MainPipeControlIn B Input
IFUPLAMainPipeControl.MainPipeControlOut
B outputs
Stage2ANormalBA: BOOL,
Stage2ABubbleBA: BOOL,
Stage3ANormalBA: BOOL,
Stage3AAbortBA: BOOL, -- carries a weakened micro to stage 3AB
Ac outputs
LoadStage1Ac: BOOL,
LoadStage2Ac: BOOL,
LoadStage3Ac: BOOL,
A outputs
RschClearAB: BOOL,
RschWaitingAB: BOOL,
Stage1BHoldingAB: BOOL,
Stage2BNormalAB: BOOL,
Stage2BAbortAB: BOOL,
Stage3BCPipeNormalAB: BOOL,
Stage3BCPipeAbortAB: BOOL,
MicroExcptJmpAB: IFUPLAMainPipeControl.MicroExcptJmp,
ExceptAB: IFUPLAMainPipeControl.Exception,
Bc outputs
NotBcLoadStage1AB: BOOL,
LoadStage1Bc: BOOL,
IFUPLAInstrDecode.InstrDecodeIn A Input
IFUPLAInstrDecode.InstrDecodeOut0
NextMacroBA: IFUPLAInstrDecode.NextMacro,
PCNextBA: IFUPLAInstrDecode.PCNext,
PCBusSrcBA: IFUPLAInstrDecode.PCBusSrc,
PCPipeSrcBA: IFUPLAInstrDecode.PCPipeSrc,
X2ALitSourceBA: IFUPLAInstrDecode.X2ALitSource,
KPadsIn0BA: BOOL,
Push0BA: BOOL,
IFUPLAInstrDecode.InstrDecodeOut1
InstStarting0BA: BOOL, -- output of instruction decode PLA
MicroCycleNextBA: IFUPLAInstrDecode.MicroCycleNext,
ProtMicroCycleBA: BOOL,
FlagSrcBA: IFUPLAInstrDecode.FlagSrc,
Pop0BA: BOOL,
DPCmndBA: Dragon.PBusCommands,
DPCmndIsRd0BA: BOOL,
DPCmndSelBA: IFUPLAInstrDecode.DPCmndSel,
IFUPLAInstrDecode.InstrDecodeOut2
ARegLtBA: IFUPLAInstrDecode.ABCSourceLt,
ARegRtBA: IFUPLAInstrDecode.ABCSourceRt,
ARegOffBA: IFUPLAInstrDecode.PlusOffset,
ARegModBA: IFUPLAInstrDecode.Mod,
IFUPLAInstrDecode.InstrDecodeOut3
BRegLtBA: IFUPLAInstrDecode.ABCSourceLt,
BRegRtBA: IFUPLAInstrDecode.ABCSourceRt,
BRegOffBA: IFUPLAInstrDecode.PlusOffset,
BRegModBA: IFUPLAInstrDecode.Mod,
IFUPLAInstrDecode.InstrDecodeOut4
KIsRtOp0BA: BOOL,
FCtlIsRtOp0BA: BOOL,
PushScBA: BOOL,
CRegLtBA: IFUPLAInstrDecode.ABCSourceLt,
CRegRtBA: IFUPLAInstrDecode.ABCSourceRt,
CRegOffBA: IFUPLAInstrDecode.MinusOffset,
CRegModBA: IFUPLAInstrDecode.Mod,
IFUPLAInstrDecode.InstrDecodeOut5
LSourceLtBA: IFUPLAInstrDecode.LSourceLt,
LSourceRtBA: IFUPLAInstrDecode.LSourceRt,
SSourceLtBA: IFUPLAInstrDecode.SSourceLt,
SSourceRtBA: IFUPLAInstrDecode.SSourceRt,
PopSaBA: BOOL,
PopSbBA: BOOL,
IFUPLAInstrDecode.InstrDecodeOut6
AluOpBA: Dragon.ALUOps,
AluOpIsOp47BA: BOOL,
CondSelBA: Dragon.CondSelects,
CondSelIsOp57BA: BOOL,
CondEffect0BA: IFUPLAInstrDecode.CondEffect,
X1ADstSLimitAc: BOOL,
X1ASrcSLimitAc: BOOL,
X1ADstStackBA: BOOL,
X1ASrcStackBA: BOOL,
X1ASrcStackLBA: BOOL,
X1ASrcStackPBA: BOOL,
XBusStackLBA: BOOL,
XBusStackEldestBA: BOOL,
CIsField0BA: BOOL,
x1ASrcSLimitBA: BOOL,
x1ADstSLimitBA: BOOL,
MicroCycle State
StateAB: Dragon.HexByte,
StateBA: Dragon.HexByte,
Literal generator
xaPipe0BA: Dragon.HexWord,
xaPipe1AB: Dragon.HexWord,
xaPipe1BA: Dragon.HexWord,
IFUSrcStatusControl.StatusControl
UserMode0AB: BOOL,
TrapsEnabled2BA: BOOL,
nextUserModeBA: BOOL,
nextTrapsEnabledBA: BOOL,
userMode: ARRAY [0..3] OF ARRAY Dragon.Phase OF BOOL,
trapsEnabled: ARRAY [0..3] OF ARRAY Dragon.Phase OF BOOL,
Procedure call stack
pStack: ARRAY [0..16) OF Dragon.HexWord,
lStack: ARRAY [0..16) OF Dragon.HexWord,
pRdBufA: Dragon.HexWord,
lRdBufA: Dragon.HexWord,
pWrtBufA: Dragon.HexWord,
lWrtBufA: Dragon.HexWord,
Program counter maintenance
PCPipe3BA: Dragon.HexWord,
PCStkTopAB: Dragon.HexWord,
PCForLogAB: Dragon.HexWord,
OpBA: [0..256),
AlphaBA: [0..256),
BetaBA: [0..256),
npcBA: Dragon.HexWord, -- latch on PCBusB
pcSum: Dragon.HexWord, -- adder output
pcBranchOSetB: Dragon.HexWord, -- mux for one arm of adder during PhB
xAB: Dragon.HexWord, -- latch on XBus
pcPipe: ARRAY [1..3] OF ARRAY Dragon.Phase OF Dragon.HexWord,
pcAltPipe: ARRAY [1..2] OF ARRAY Dragon.Phase OF Dragon.HexWord,
pcAB: Dragon.HexWord, -- the PC for this instruction
pcBA: Dragon.HexWord, -- the PC for this instruction
targetPCBA: Dragon.HexWord,
L / S Register maintenance
SAB: Dragon.HexByte,
LAB: Dragon.HexByte,
SBA: Dragon.HexByte,
LBA: Dragon.HexByte,
LFPipe3BA: Dragon.HexWord,
LFStkTopAB: Dragon.HexWord,
DeltaSBA: Dragon.HexByte,
EStkOverflow1BA: BOOL,
sLimitAB: Dragon.HexByte,
sPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
lPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
-Pipe[i] is the value of the register to be recovered if the microinstruction at pipeline level i "fails". This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.
A,B,C register addressing
A1IsC2B: BOOL, -- match lines, precharge during 1A
A1IsC3B: BOOL,
B1IsC2B: BOOL,
B1IsC3B: BOOL,
aPipe: ARRAY [0..1] OF ARRAY Dragon.Phase OF Dragon.HexByte,
bPipe: ARRAY [0..1] OF ARRAY Dragon.Phase OF Dragon.HexByte,
cPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
a1BEarly1AB: Dragon.HexByte, -- predicts 1BA one phase early
b1BEarly1AB: Dragon.HexByte, -- predicts 1BA one phase early
Scan Register
plaBuffers: ARRAY IFUPLA.PLAs OF ARRAY IFUPLA.Sense OF REF ← ALL[ALL[NIL]],
plaOffsets: ARRAY IFUPLA.PLAs OF ARRAY IFUPLA.Sense OF INTEGER ← ALL[ALL[-1]],
drShWt: BOOL,
drShifterAB: BitSeq,
drShifterBA: BitSeq,
IFUSrcControlPipe.ControlPipe
PushPendingAB: BOOL,
PopPendingAB: BOOL,
EUAluOp0BA: Dragon.ALUOps, -- After Muxing
CondSel0BA: Dragon.CondSelects, -- After Muxing
DPCmnd0BA: Dragon.PBusCommands, -- After Muxing
KIsRtOp1BA: BOOL,
EStkOverflow2BA: BOOL,
InstFault2BA: BOOL,
FCtlIsRtOp1BA: BOOL,
Push2AB: BOOL,
Push3AB: BOOL,
Pop3AB: BOOL,
X2ASrcLit1BA: BOOL,
KPadsIn3BA: BOOL,
InstStarting2BA: BOOL,
EUSt3AIsCBus2BA: BOOL,
CondEffect1BA: IFUPLAMainPipeControl.CondEffect,
CondEffect2BA: IFUPLAMainPipeControl.CondEffect,
CIsField2AB: BOOL,
CIsField3AB: BOOL,
DPCmndIsRd2BA: BOOL,
DPCmnd3A: Dragon.PBusCommands, -- The Si needs to clear this
EUCondSel3AB: Dragon.CondSelects,
CondEffect2AB: IFUPLAMainPipeControl.CondEffect,
ctlPipe1AB:
RECORD [
-- state
x2ASrcLit: BOOL,
push: BOOL,
pop: BOOL,
kPadsIn: BOOL,
dpCmnd: Dragon.PBusCommands,
aluOp: Dragon.ALUOps,
kIsRtOp: BOOL,
condSel: Dragon.CondSelects,
condEffect: IFUPLAMainPipeControl.CondEffect,
fCtlIsRtOp: BOOL,
cIsField: BOOL,
rdFromPBus: BOOL,
writeToPBus: BOOL,
instFault: BOOL,
firstMicro: BOOL ],
ctlPipe1BA:
RECORD [
x2ASrcLit: BOOL,
push: BOOL,
pop: BOOL,
kPadsIn: BOOL,
dpCmnd: Dragon.PBusCommands,
aluOp: Dragon.ALUOps,
kIsRtOp: BOOL,
condSel: Dragon.CondSelects,
condEffect: IFUPLAMainPipeControl.CondEffect,
fCtlIsRtOp: BOOL,
cIsField: BOOL,
rdFromPBus: BOOL,
writeToPBus: BOOL,
instFault: BOOL,
firstMicro: BOOL ],
ctlPipe2AB:
RECORD [
x2ASrcLit: BOOL,
push: BOOL,
pop: BOOL,
kPadsIn: BOOL,
dpCmnd: Dragon.PBusCommands,
aluOp: Dragon.ALUOps,
condSel: Dragon.CondSelects,
condEffect: IFUPLAMainPipeControl.CondEffect,
cIsField: BOOL,
rdFromPBus: BOOL,
writeToPBus: BOOL,
eStkOverflow: BOOL,
st3AisCBus: BOOL,
instFault: BOOL,
firstMicro: BOOL ],
ctlPipe2BA:
RECORD [
push: BOOL,
pop: BOOL,
kPadsIn: BOOL,
dpCmnd: Dragon.PBusCommands,
condSel: Dragon.CondSelects,
condEffect: IFUPLAMainPipeControl.CondEffect,
cIsField: BOOL,
rdFromPBus: BOOL,
writeToPBus: BOOL,
eStkOverflow: BOOL,
st3AisCBus: BOOL,
instFault: BOOL,
firstMicro: BOOL ],
ctlPipe3AB:
RECORD [
push: BOOL,
pop: BOOL,
kPadsIn: BOOL,
dpCmnd: Dragon.PBusCommands,
condSel: Dragon.CondSelects,
cIsField: BOOL,
rdFromPBus: BOOL,
writeToPBus: BOOL ],
ctlPipe3BA:
RECORD [
kPadsIn: BOOL,
cIsField: BOOL ],
Logging
AReg0BA: Dragon.HexByte,
BReg0BA: Dragon.HexByte,
CReg0BA: Dragon.HexByte,
log: IO.STREAM,
cycle: INT,
instrCount: INT,
opPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF LogPipeState,
bHigh: BOOL, -- for noting the falling edge of B
last: QPh,
firstMicroOfMacro: LogPipeState,
dpRejectedAB: BOOL,
dpFaultedAB: BOOL,
doTrap3BA: BOOL,
xbusBCopy: Dragon.HexWord,
logRegistersB: BOOL,
interruptPending: BOOL,
trapped: BOOL
];
CreateIFU:
PROC [ typeData:
REF IFUTypeData, fullIFU, quickIFU:
BOOL ←
FALSE ]
RETURNS [ ct: Core.CellType ];
IFUInconsistent: ERROR;
ModuleSimProc: TYPE = PROC [ p: Ports.Port, state: IFUState ];
ModSimRec: TYPE = RECORD [proc: ModuleSimProc];
ModSim: TYPE = REF ModSimRec;
END.