IFU2.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
McCreight, June 6, 1986 4:25:48 pm PDT
DIRECTORY CacheOps, Core, Dragon, DragOpsCross, IFUPLA, IFUPLAFetchControl, IFUPLAFetchPreDecode, IFUPLAMainControl, IFUPLAInstrDecode, IO, Ports;
IFU2: CEDAR DEFINITIONS
= BEGIN
CurrentIFUVersion: Dragon.HexByte = 1;
QuadPhase: TYPE = {a, postA, b, postB};
II: TYPE = {
KBus, EUAluOp2AB, EUCondSel2AB, EUCondition2B, EURes3BisPBus3AB, EUWriteToPBus3AB, -- EU
DPCmdA, DPRejectB, DPFaultB, -- DCache
IPData, IPCmdA, IPRejectB, IPFaultB, -- ICache
DrShA, DrShB, DrShRd, DrShWt, DrShIn, DrShOut, -- Debugging shifter
PhA, PhB, ResetAB, RescheduleAB -- control/timing
};
MicroInstDisposition: TYPE = {unready, valid, interlocked, killed2b, killed3a, killed3b};
LogPipeState: TYPE = RECORD [
pc: Dragon.HexWord,
op: DragOpsCross.Inst ← x374B,
alpha, beta, gamma, delta: Dragon.HexByte ← 0,
microCyc: NAT ← 0,
disposition: MicroInstDisposition ← unready
];
RegAddrRec: TYPE = MACHINE DEPENDENT RECORD [
.. this will be LOOPHOLE'd to LONG CARDINAL, so its low-order word must appear first, as does that of a LONG CARDINAL (sigh!)
cAddr (0: 0..7): Dragon.HexByte,
st3AisC (0: 8..8): BOOL,
aluLeftSrc (0: 9..10): Dragon.ALULeftSources,
aluRightSrc (0: 11..13): Dragon.ALURightSources,
storeSrc (0: 14..15): Dragon.Store2ASources,
aAddr (1: 0..7): Dragon.HexByte,
bAddr (1: 8..15): Dragon.HexByte
];
BitSeq: TYPE = RECORD [ -- for debugging shift register
size: [0..1024] ← 1024,
bits: PACKED ARRAY [0..1024) OF BOOL
];
BasicInst: TYPE = RECORD [
cycle:   INT,
instr:   INT,
trapped:  BOOL, -- this instruction was aborted
trapPC:  Dragon.HexWord, -- if aborted, then why?
pc:   Dragon.HexWord,
op:   DragOpsCross.Inst,
alpha, beta, gamma, delta: Dragon.HexByte
];
GetLogProc: TYPE = PROC [ data: REF ANY ] RETURNS [ s: Core.STREAM ];
GetCycleProc: TYPE = PROC [ data: REF ANY ] RETURNS [ cycle: INT ];
CheckSynchProc: TYPE = PROC [ data: REF ANY, basicInst: BasicInst ] RETURNS [ deltaInstrCount: INT ← 1 ];
IFUTypeData: TYPE = RECORD [
data: REF ANY,
getLog: GetLogProc ← NIL,
getCycle: GetCycleProc ← NIL,
checkSynch: CheckSynchProc ← NIL
];
IFUState: TYPE = RECORD [
data: REF IFUTypeData,
public: Core.Wire,
oldP: Ports.Port,
maxConvergencePasses: NAT,
oldState: REF IFUState,
ph: QuadPhase ← a, -- for simulation only, not represented in hardware
XBus: Dragon.HexWord, -- main data bus within IFU, sometimes connects to KBus
ResetBA: BOOL,
Instruction prefetcher
PCBusB: Dragon.HexWord,
MacroJumpBA: BOOL,
GetNextInstBA: BOOL,
InstReadyAB: BOOL,
IPFaulted0BA: BOOL,
IncrPFetchAddrBA: BOOL,
FetchWtB: IFUPLAFetchControl.WtIndexCtl,
FetchingAB: BOOL,
BufBytesOccM1A: [0..32),
IBufWrtWdBc: PACKED ARRAY [0..4) OF BOOL,
IBufRdByteAc: PACKED ARRAY [0..16) OF BOOL,
OpLengthAB: [0..8),
OpLengthBA: [0..8),
OpAB: [0..256),
AlphaAB: [0..256),
BetaAB: [0..256),
GammaAB: [0..256),
DeltaAB: [0..256),
JumpOffsetSelAB: IFUPLAFetchPreDecode.JumpOffsetSel,
jumpPendingAB: BOOL,
jumpPendingBA: BOOL,
newFetchBA: BOOL,
fetchingBA: BOOL,
faultedBA: BOOL,
faultedAB: BOOL,
bufBytesOccM1AB: [0..32),
preOpA: Dragon.HexByte,
preAlphaA: Dragon.HexByte,
preBetaA: Dragon.HexByte,
preGammaA: Dragon.HexByte,
preDeltaA: Dragon.HexByte,
iBuf: ARRAY [0..16) OF Dragon.HexByte,
wtAB: [0..8),
wtBA: [0..8),
rdAB: [0..32),
rdBA: [0..32),
fetchAddrBA: Dragon.HexWord,
fetchAddrAB: Dragon.HexWord,
Instruction Decoding PLA
StateAB: [0..256) ← 0, -- auxiliary input to instruction decode PLA
PushPendingAB: BOOL,
PopPendingAB: BOOL,
UserMode0AB: BOOL,
InstStarting0BA: BOOL, -- output of instruction decode PLA
MicroCycleNextBA: IFUPLAInstrDecode.MicroCycleNext,
PCNextBA: IFUPLAInstrDecode.PCNext,
PCBusSrcB: IFUPLAInstrDecode.PCBusSrc,
PCPipeSrcBA: IFUPLAInstrDecode.PCPipeSrc,
Push0BA: BOOL,
Pop0BA: BOOL,
X1ASrcStackBA: BOOL,
X1ADstStackBA: BOOL,
XBusStackEldestBA: BOOL,
XBusStackLBA: BOOL,
X1ASrcSLimitAc: BOOL,
X1ADstSLimitAc: BOOL,
X2ASrcStatusBA: BOOL,
X1ADstStatusBA: BOOL,
ASourceLtBA: IFUPLAInstrDecode.ABCSourceLt,
ASourceRtBA: IFUPLAInstrDecode.ABCSourceRt,
ASourceOffBA: IFUPLAInstrDecode.PlusOffset,
ASourceModBA: IFUPLAInstrDecode.Mod,
BSourceLtBA: IFUPLAInstrDecode.ABCSourceLt,
BSourceRtBA: IFUPLAInstrDecode.ABCSourceRt,
BSourceOffBA: IFUPLAInstrDecode.PlusOffset,
BSourceModBA: IFUPLAInstrDecode.Mod,
CSourceLtBA: IFUPLAInstrDecode.ABCSourceLt,
CSourceRtBA: IFUPLAInstrDecode.ABCSourceRt,
CSourceOffBA: IFUPLAInstrDecode.MinusOffset,
CSourceModBA: IFUPLAInstrDecode.Mod,
CIsField0BA: BOOL,
LSourceLtBA: IFUPLAInstrDecode.LSourceLt,
LSourceRtBA: IFUPLAInstrDecode.LSourceRt,
SSourceLtBA: IFUPLAInstrDecode.SSourceLt,
SSourceRtBA: IFUPLAInstrDecode.SSourceRt,
PopSa0BA: BOOL,
PopSb0BA: BOOL,
PushSc0BA: BOOL,
X2ALitSourceBA: IFUPLAInstrDecode.X2ALitSource,
KIsRtOp0BA: BOOL,
FCtlIsRtOp0BA: BOOL,
EUAluOp0BA: Dragon.ALUOps,
EUCondSel0BA: Dragon.CondSelects,
EUCondEffect0BA: IFUPLAInstrDecode.CondEffect,
DPCmnd0BA: Dragon.PBusCommands,
DPCmndRd0BA: BOOL,
ClearTrapsEnbledBA: BOOL,
ClearUserModeBA: BOOL,
KPadsIn0BA: BOOL,
X2ASrcLit0BA: BOOL, -- derived
x1ASrcSLimitBA: BOOL,
x1ADstSLimitBA: BOOL,
Main Control
DPRejectedBA: BOOL, -- input to main control PLA
dpFaultedBA: BOOL,
EUCondEffect1BA: IFUPLAMainControl.CondEffect,
EUCondEffect2BA: IFUPLAMainControl.CondEffect,
Stage1BHoldBA: BOOL,
InstStarting2BA: BOOL,
IPFaulted2BA: BOOL,
TrapsEnbled2BA: BOOL,
RschWaiting2BA: BOOL,
IStkNearlyFullBA: BOOL,
EStkOverflow2BA: BOOL,
Push2BA: BOOL,
willBeProtMicroCycBA: BOOL,
euCondition2BA: BOOL,
abortPipeAB: BOOL, -- output from main control PLA
MicroExcptJmpAB: IFUPLAMainControl.MicroExcptJmp,
ExceptionCodeAB: IFUPLAMainControl.ExceptionCode,
wantNewMicro0AB, wantNewMicro0BA: BOOL, -- state
stage1BHoldingAB: BOOL,
abortPipeBA: BOOL,
stage2FailedBA: BOOL,
microCycleAB: Dragon.HexByte,
microCycleBA: Dragon.HexByte,
LoadStage1Ac: BOOL, -- Pipeline multiplex controls and latch clocks
LoadStage1Bc: BOOL,
LoadStage2Ac: BOOL,
BubbleStage2A1BA: BOOL,
NormalStage2A1BA: BOOL,
AbortStage2B2AB: BOOL,
NormalStage2B2AB: BOOL,
LoadStage3Ac: BOOL,
AbortStage3A2BA: BOOL, -- carries a weakened micro to stage 3AB for state-saving
NormalStage3A2BA: BOOL,
Control pipeline
EUSt3AisCBus1BA: BOOL, -- additional inputs
EStkOverflow1BA: BOOL,
X2ASrcLit1BA: BOOL, -- additional outputs
KIsRtOp1BA: BOOL,
KPadsIn3BA: BOOL,
Push3BA: BOOL,
Pop3BA: BOOL,
FCtlIsRtOp1BA: BOOL,
CIsField2AB: BOOL,
CIsField3AB: BOOL,
DPCmnd3A: Dragon.PBusCommands,
DPCmndRd2BA: BOOL,
DPCmndRd3BA: BOOL,
EUCondSel3AB: Dragon.CondSelects,
EUSt3AisCBus2BA: BOOL,
EUCondEffect2AB: IFUPLAMainControl.CondEffect,
ctlPipe1AB: RECORD [ -- state
x2ASrcLit:  BOOL,
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
aluOp:   Dragon.ALUOps,
kIsRtOp:   BOOL,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
fCtlIsRtOp:   BOOL,
cIsField: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe1BA: RECORD [
x2ASrcLit:  BOOL,
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
aluOp:   Dragon.ALUOps,
kIsRtOp:   BOOL,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
fCtlIsRtOp:   BOOL,
cIsField: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe2AB: RECORD [
x2ASrcLit:  BOOL,
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
aluOp:   Dragon.ALUOps,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
cIsField: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
eStkOverflow: BOOL,
st3AisCBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe2BA: RECORD [
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
condSel:   Dragon.CondSelects,
condEffect:  IFUPLAMainControl.CondEffect,
cIsField: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL,
eStkOverflow: BOOL,
st3AisCBus:  BOOL,
instFault:   BOOL,
firstMicro:  BOOL
],
ctlPipe3AB: RECORD [
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
dpCmnd:   Dragon.PBusCommands,
condSel:   Dragon.CondSelects,
cIsField: BOOL,
res3BisPBus:  BOOL,
writeToPBus:  BOOL
],
ctlPipe3BA: RECORD [
push:    BOOL,
pop:    BOOL,
kPadsIn:   BOOL,
cIsField: BOOL,
res3BisPBus:  BOOL
],
Literal generator
xaPipe0BA: Dragon.HexWord,
xaPipe1AB: Dragon.HexWord,
xaPipe1BA: Dragon.HexWord,
Status register maintenance
RescheduleBA: BOOL,
status: ARRAY Dragon.Phase OF DragOpsCross.IFUStatusRec,
rsPipe: ARRAY Dragon.Phase OF BOOL,
x2ASrcStatus: ARRAY Dragon.Phase OF BOOL,
statPipe: ARRAY Dragon.Phase OF DragOpsCross.IFUStatusRec,
Procedure call stack
DifBA: [0..32),
AdjTosA: BOOL,
AddendIsOnesA: BOOL,
CarryIsOneA: BOOL,
TosAB: [0..32),
BosAB: [0..32),
StkLdPAc: PACKED ARRAY [0..16) OF BOOL,
StkLdLAc: PACKED ARRAY [0..16) OF BOOL,
StkRdAc: PACKED ARRAY [0..16) OF BOOL,
stkLdPBA: PACKED ARRAY [0..16) OF BOOL,
stkLdLBA: PACKED ARRAY [0..16) OF BOOL,
stkRdBA: PACKED ARRAY [0..16) OF BOOL,
tosAB, tosBA: [0..32),
bosAB, bosBA: [0..32),
difBA: [0..32),
pStack: ARRAY [0..16) OF Dragon.HexWord,
pRdBufA, pWrtBufA: Dragon.HexWord,
lStack: ARRAY [0..16) OF Dragon.HexByte,
lRdBufA, lWrtBufA: Dragon.HexByte,
Program counter maintenance
PCPipe3BA: Dragon.HexWord,
PCStkTopAB: Dragon.HexWord,
OpBA: [0..256),
AlphaBA: [0..256),
BetaBA: [0..256),
PCForLogAB: Dragon.HexWord,
npcBA: Dragon.HexWord, -- latch on PCBusB
pcSum: Dragon.HexWord, -- adder output
pcBranchOSetB: Dragon.HexWord, -- mux for one arm of adder during PhB
xAB: Dragon.HexWord, -- latch on XBus
pcPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexWord,
pcAltPipe: ARRAY [0..2] OF ARRAY Dragon.Phase OF Dragon.HexWord,
pcAB, pcBA: Dragon.HexWord, -- the PC for this instruction
targetPCBA: Dragon.HexWord,
dpFaultAB, dpFaultBA: Dragon.PBusFaults,
L / S Register maintenance
SAB: Dragon.HexByte,
LAB: Dragon.HexByte,
LPipe3BA: Dragon.HexByte,
LStkTopAB: Dragon.HexByte,
DeltaSBA: Dragon.HexByte,
lBA, lAB: Dragon.HexByte,
lPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
lPipe[i] is the value of the L register to be recovered if the microinstruction at pipeline level i "fails". This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.
sBA, sAB: Dragon.HexByte,
sPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
sPipe[i] is the value of the S register to be recovered if the microinstruction at pipeline level i "fails". This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.
sLimitAB:    Dragon.HexByte,
A,B,C register addressing
aRegIsC2B: BOOL, -- match lines, precharge during 1A, eval during 1B
aRegIsC3B: BOOL,
bRegIsC2B: BOOL,
bRegIsC3B: BOOL,
aPipe: ARRAY [0..1] OF ARRAY Dragon.Phase OF Dragon.HexByte,
a1BEarly1AB: Dragon.HexByte, -- predicts 1BA one phase early
bPipe: ARRAY [0..1] OF ARRAY Dragon.Phase OF Dragon.HexByte,
b1BEarly1AB: Dragon.HexByte, -- predicts 1BA one phase early
cPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte,
Pipeline interlock detection
EUAluLeftSrc1B: Dragon.ALULeftSources,
EUAluRightSrc1B: Dragon.ALURightSources,
EUStore2ASrc1B: Dragon.Store2ASources,
Debugging state shifter
drShWt: BOOL,
plaBuffers: ARRAY IFUPLA.PLAs OF ARRAY IFUPLA.Sense OF REF ← ALL[ALL[NIL]],
plaOffsets: ARRAY IFUPLA.PLAs OF ARRAY IFUPLA.Sense OF INTEGER ← ALL[ALL[-1]],
drShifterAB: BitSeq,
drShifterBA: BitSeq,
Logging
AReg0BA, BReg0BA, CReg0BA: Dragon.HexByte,
log: IO.STREAM,
cycle: INT,
instrCount: INT,
opPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF LogPipeState,
bHigh:     BOOL, -- for noting the falling edge of B
last:       QuadPhase,
firstMicroOfMacro:  LogPipeState,
dpRejectedAB:   BOOL,
dpFaultedAB:   BOOL,
doTrap3BA:    BOOL,
xbusBCopy:    Dragon.HexWord,
logRegistersB:   BOOL,
interruptPending:  BOOL,
trapped:     BOOL
]
;
IFU: PROC [ typeData: REF IFUTypeData ] RETURNS [ ct: Core.CellType ];
IFUInconsistent: ERROR;
NewIFUState: PROC [ pattern: REF IFUState ← NIL ] RETURNS [ REF IFUState ];
ModuleSimProc: TYPE = PROC [ p: Ports.Port, state: REF IFUState ];
ModSimRec: TYPE = RECORD [proc: ModuleSimProc];
ModSim: TYPE = REF ModSimRec;
END.