Directory Dragon, DragOpsCross, DragonMicroPLA; Imports BitOps, Dragon, DragonIFU; Cedar depth: NAT = 16; gap: NAT = 5; lwx: NAT = 7; lpx: NAT = 32-lwx; m1:NAT = depth-1; ; IStack: CELL [ PushLevel3BA BOOL, IStkTooFullA >BOOL, Lev0BaddrBA Dragon.Assert[FALSE, "IStack Underflowed"]; =0 => {IStkEmptyA _ TRUE; IStkTooFullA _ FALSE}; IN(0..depth-gap] => {IStkEmptyA _ FALSE; IStkTooFullA _ FALSE}; ENDCASE => {IStkEmptyA _ FALSE; IStkTooFullA _ TRUE}; iStk[(top+1) MOD depth] _ [ p:Dragon.LFD[Lev3PBA], l:BitOps.ECFW[Lev3LBA, lwx, 0, lwx] ]; SELECT TRUE FROM b0 IN [ifuYoungestL..ifuEldestPC] => { Dragon.Assert[ NOT wasEmpty ]; SELECT b0 FROM ifuYoungestL => XBus _ BitOps.ICID[iStk[top].l, [0,0], 32, lpx, lwx]; ifuYoungestPC => XBus _ Dragon.LTD[iStk[top].p]; ifuEldestL => XBus _ BitOps.ICID[iStk[bot].l, [0,0], 32, lpx, lwx]; ifuEldestPC => XBus _ Dragon.LTD[iStk[bot].p]; ENDCASE => NULL}; -- Not an IFU stack register c3 IN [ifuYoungestL..ifuEldestPC] => SELECT c3 FROM ifuYoungestL => iStk[top].l _ BitOps.ECFD[XBus, 32, lpx, lwx]; ifuYoungestPC => iStk[top].p _ Dragon.LFD[XBus]; ifuEldestL => iStk[bot].l _ BitOps.ECFD[XBus, 32, lpx, lwx]; ifuEldestPC => iStk[(bot+m1) MOD depth].p _ Dragon.LFD[XBus]; ENDCASE => NULL; -- Not an IFU stack register ENDCASE => NULL; -- nothing special happening END; IF PhB THEN BEGIN FOR i: NAT IN [0..depth) DO iStk[i].valid[b] _ (Valid[i] AND NOT popYoungestA AND NOT popEldestA) OR (Valid[i] AND Valid[i+m1] AND NOT popYoungestA) OR (Valid[i] AND Valid[i+1] AND NOT popEldestA) OR (Valid[i] AND Valid[i+1] AND Valid[i+m1]) OR (Valid[i+1 ] AND pushEldestA) OR (Valid[i+m1] AND pushYoungestA) OR (wasEmpty AND pushEldestA AND i=0) OR (wasEmpty AND pushYoungestA AND i=1); ENDLOOP; FOR i: NAT IN [0..depth) DO IF iStk[i].valid[b] AND NOT iStk[(i+1) MOD depth].valid[b] -- top AND XBSourceBA = iStackPC THEN { Dragon.Assert[ NOT IStkEmptyA ]; XBus _ Dragon.LTD[iStk[i].p]}; ENDLOOP; END; ENDCELL fIStack.rose Copyright c 1984 by Xerox Corporation. All rights reserved. Last edited by: McCreight, April 9, 1984 1:34:58 pm PST Last edited by: Curry, August 21, 1984 12:35:43 pm PDT Interface within IFU Serial debugging interface Timing and housekeeping interface Note: When a signal ends in an x, it is calculated during x and stable during x'. Êo˜šÐbl ™ Jšœ Ïmœ1™Jšœ& œ˜0Jšœ$ œ˜=Jšœ œ œ˜>Jš œ ¡˜/——Jš œ ¡˜-—Jš œ˜J˜—š œ ˜ Jš ˜J˜š œ œ œ  ˜šœ˜Jš œ  œ œ œ œ  ˜5Jšœ  œ  œ œ ˜2Jšœ  œ  œ œ  ˜/Jšœ  œ  œ ˜,Jšœ œ ˜!Jšœ  œ ˜"Jšœ  œ œ ˜&Jšœ  œ œ˜%—Jš œ˜—J˜š œ œ œ  ˜š œ˜Jš œ œ  œ¡˜-š œ œ˜ Jšœ œ˜ Jšœ œ ˜——Jš œ˜—Jš œ˜J˜———Jš ˜J˜J˜—…—*ÿ