Directory DragonMicroPLA;
Imports Dragon, DragonIFU;

IPipe: CELL [

XBus						=INT[32],

Lev0PA					<INT[32],
Lev0LA					<INT[8],
Lev0SA					<INT[8],

Lev0AaddrBA			<INT[8],
Lev0BaddrBA			<INT[8],
Lev0CaddrA				<INT[8],

Lev0AluRtIsKBA		<BOOL,
Lev0AluOpBA			<EnumType["Dragon.ALUOps"],
Lev0CondSelBA			<EnumType["Dragon.CondSelects"],
Lev0CondEffectBA		<EnumType["DragonMicroPLA.CondEffect"],

Lev0IStackPostEffectBA	<EnumType["DragonMicroPLA.IStackPostEffect"],
Lev0ITrapPostEffectBA	<EnumType["DragonMicroPLA.ITrapPostEffect"],
Lev0EuPBusCmdBA		<EnumType["Dragon.PBusCommands"],

Lev2CondSelBA			>EnumType["Dragon.CondSelects"],
Lev3CaddrBA			>INT[8],

XBSourceBA				<EnumType["DragonMicroPLA.XBSource"],

DontBypassBA			<BOOL,
KillPipeAB				<BOOL,
PushPendingAB			>BOOL,
PopPendingAB			>BOOL,
ITrapEffectPendingAB	>EnumType["DragonMicroPLA.ITrapPostEffect"],
Lev3ITrapEffectBA		>EnumType["DragonMicroPLA.ITrapPostEffect"],
DelayACycleAB			>BOOL,
Lev2CondEffectBA		>EnumType["DragonMicroPLA.CondEffect"],

IStkPushBA  			>BOOL,
IStkPopBA				>BOOL,
Lev3PBA					>INT[32],
Lev3LBA					>INT[8],

KBus						=INT[32],	-- PhA bidirectional, PhB A,B,C to EU

EUAluLeftisR1BA		>BOOL,	-- Left Default is aRam	1B
EUAluLeftisR3BA		>BOOL,	-- Left Default is aRam	1B

EUAluRightisR1BA			>BOOL,	-- Right Default is bRam	1B
EUAluRightisR3BA			>BOOL,	-- Right Default is bRam	1B
EUAluRightisKBA			>BOOL,	-- Right Default is bRam	1B

EUS1isR1BA				>BOOL,	-- Default is bRam			1B
EUS1isR3BA				>BOOL,	-- Default is bRam			1B

EUAluOpAB				>EnumType["Dragon.ALUOps"],		-- 2A
EUCondSelAB			>EnumType["Dragon.CondSelects"],	-- 2A

EUR2isR3BA				>BOOL,	-- Default is R1				2B
EUS3isR3BA				>BOOL,	-- Default is S2				2B
EUTrapBA				>BOOL,	-- Trap on conditon		2B
EUHoldCarryBA			>BOOL,	-- Preserve carry

EUR3isR2AB				>BOOL,	-- Default is RData			3A
EUWriteToPBusAB		>BOOL,	-- Data direction			3A
EUCheckPParityAB		>BOOL,	-- Yes for non-FP Fetch	3A
FPCSLoadBA			>EnumType["DragonFP.CSLoad"],
FPCSUAluBA		>EnumType["DragonFP.CSUnload"],
FPCSUMultBA		>EnumType["DragonFP.CSUnload"],

EPCmdA				>EnumType["Dragon.PBusCommands"],
EPRejectB			<BOOL,
ResetAB			<BOOL,
DHoldAB			<BOOL,
DShiftAB  		<BOOL,
DExecuteAB		<BOOL,
DNSelectAB		<BOOL,
DDataInAB		<BOOL,
DDataOutAB		=BOOL,
RescheduleAB	<BOOL,
PhA				<BOOL,
PhB				<BOOL
]

State
delayed1:	ARRAY Dragon.Phase OF	DragonIFU.Level1,
level1:	ARRAY Dragon.Phase OF	DragonIFU.Level1,
level2:	ARRAY Dragon.Phase OF	DragonIFU.Level2,
level3:	ARRAY Dragon.Phase OF	DragonIFU.Level3,

lastCycleDelayedBA		:BOOL,
level3RejectingBA		:BOOL,
killPipeBA				:BOOL,
dHoldBA					:BOOL

EvalSimple

Bypass: PROC[
next1: DragonIFU.Level1,
lev1: DragonIFU.Level1,
lev2: DragonIFU.Level2,
lev3: DragonIFU.Level3,
noBypassing: BOOL]
RETURNS[interlock: BOOL, adjustedNext1: DragonIFU.Level1] = {
field		:Dragon.HexByte _ DragonIFU.PRtoByte[euField];
read1		:BOOL _ DragonIFU.IsRdCmd	[next1.euPBus];
read2		:BOOL _ DragonIFU.IsRdCmd	[lev1.euPBus];
ac2  		:BOOL _ next1.a = lev1.c;
ac3  		:BOOL _ next1.a = lev2.c;
bc2  		:BOOL _ next1.b = lev1.c;
bc3  		:BOOL _ next1.b = lev2.c;
passRt  	:BOOL _
next1.aluOp=Or AND next1.a=(DragonIFU.PRtoByte[euConstant]+0) AND  -- EU ALU nop
NOT DragonIFU.IsFPCmd[next1.euPBus]; --  can't bypass address 
interlock _ read2 AND (ac2 OR (bc2 AND NOT (next1.aluRt=k OR passRt)));
interlock _ interlock OR
next1.aluOp=FOP AND (lev1.c=field OR lev2.c=field OR lev3.c=field);
adjustedNext1 _ IF interlock THEN [] ELSE next1;
IF NOT noBypassing AND NOT interlock THEN { OPEN adjustedNext1;
aluLt _ IF ac2 THEN r1 ELSE IF ac3 THEN r3 ELSE aluLt;
aluRt _ IF next1.aluRt=k THEN aluRt
ELSE IF bc2 AND NOT read2 THEN r1
ELSE IF bc3 THEN r3 ELSE aluRt;
store1 _ IF next1.aluRt#k THEN store1  -- Write to EU => =k
ELSE IF bc2 AND NOT read2 THEN r1
ELSE IF bc3 THEN r3 ELSE store1;
result2 _ IF bc2 AND passRt THEN r3 ELSE result2;
store3 _ IF bc2 THEN r3 ELSE store3;
result3 _ IF read1 THEN rdata ELSE result3;
} };


IF PhA AND NOT dHoldBA THEN {

pipeInterlock:BOOL _ FALSE;

input: DragonIFU.Level1 _ [
a  		: Lev0AaddrBA,
b  		: Lev0BaddrBA,
aluLt  	: aRam,
aluRt  	: IF Lev0AluRtIsKBA THEN k ELSE bRam,
store1		: bRam,
ka			: Dragon.LFD[XBus],
aluOp		: Lev0AluOpBA,
condSel	: Lev0CondSelBA,
condOp	: Lev0CondEffectBA,
result2  	: r1,
store3		: s2,
euPBus	: Lev0EuPBusCmdBA,
result3  	: IF DragonIFU.IsRdCmd[Lev0EuPBusCmdBA] THEN rdata ELSE r2,
c			: Lev0CaddrA,
iStackOp	: Lev0IStackPostEffectBA,
iTrapOp	: Lev0ITrapPostEffectBA,
p  		: Dragon.LFD[Lev0PA],
l  			: Lev0LA,
s  			: Lev0SA
];

IF killPipeBA
THEN {delayed1[a] _ level1[a] _ []; level2[a] _ []; level3[a] _ []}
ELSE IF level3RejectingBA
THEN {
level1[a] _ level1[b];
level2[a] _ level2[b];
level3[a] _ level3[b];
IF lastCycleDelayedBA
THEN delayed1[a] _ delayed1[b]
ELSE delayed1[a] _ input }
ELSE {
IF lastCycleDelayedBA
THEN {
delayed1[a] _ delayed1[b];
[pipeInterlock , level1[a]]
_ Bypass[delayed1[b],	level1[b], level2[b], level3[b], DontBypassBA] }
ELSE {
delayed1[a] _ input;
[pipeInterlock , level1[a]]
_ Bypass[input,		level1[b], level2[b], level3[b], DontBypassBA] };
level2[a].ka			_ level1[b].ka;
level2[a].aluOp		_ level1[b].aluOp;
level2[a].condSel	_ level1[b].condSel;
level2[a].condOp	_ level1[b].condOp;
level2[a].result2  	_ level1[b].result2;
level2[a].store3		_ level1[b].store3;
level2[a].euPBus		_ level1[b].euPBus;
level2[a].result3  	_ level1[b].result3;
level2[a].c  			_ level1[b].c;
level2[a].iStackOp	_ level1[b].iStackOp;
level2[a].iTrapOp	_ level1[b].iTrapOp;
level2[a].p  			_ level1[b].p;
level2[a].l  			_ level1[b].l;
level2[a].s  			_ level1[b].s;

level3[a].euPBus		_ level2[b].euPBus;
level3[a].result3		_ level2[b].result3;
level3[a].c  			_ level2[b].c;
level3[a].iStackOp	_ level2[b].iStackOp;
level3[a].iTrapOp	_ level2[b].iTrapOp;
level3[a].p  			_ level2[b].p;
level3[a].l  			_ level2[b].l;
level3[a].s  			_ level2[b].s;
};

PushPendingAB _  delayed1[a].iStackOp=push OR
level1[a].iStackOp=push OR
level2[a].iStackOp=push OR
level3[a].iStackOp=push;
PopPendingAB _  delayed1[a].iStackOp=pop OR
level1[a].iStackOp=pop OR
level2[a].iStackOp=pop OR
level3[a].iStackOp=pop;

ITrapEffectPendingAB _  IF delayed1[a].iTrapOp#none
THEN delayed1[a].iTrapOp
ELSE IF level1[a].iTrapOp#none
THEN level1[a].iTrapOp
ELSE IF level2[a].iTrapOp#none
THEN level2[a].iTrapOp
ELSE level3[a].iTrapOp;

DelayACycleAB _ level3RejectingBA OR pipeInterlock;
EUAluOpAB				_ level2[a].aluOp;
EUCondSelAB			_ level2[a].condSel;

EPCmdA					_ IF level3RejectingBA THEN NoOp ELSE level2[b].euPBus;

EUWriteToPBusAB	_ DragonIFU.IsWtCmd[level3[a].euPBus];
EUCheckPParityAB	_ EUWriteToPBusAB AND NOT DragonIFU.IsFPCmd[level3[a].euPBus];
EUR3isR2AB			_ level3[a].result3=r2;
IF DragonIFU.BytetoPR[Lev3CaddrBA] IN [ifuXBus..ifuLast]
THEN	XBus _ KBus
ELSE {
IF DragonIFU.BytetoPR[Lev0BaddrBA] = ifuLevel3LS
THEN  XBus _ Dragon.LTD[level3[b].s*256 + level3[b].l];
IF level2[b].euPBus=StoreFP
THEN	KBus _ Dragon.LTD[level2[b].ka]
ELSE	KBus _ Dragon.LTD[level1[b].ka] } };
IF PhB THEN dHoldBA _ DHoldAB;

IF PhB AND NOT DHoldAB THEN {
delayed1[b]	_ IF KillPipeAB THEN [] ELSE delayed1[a];
level1[b]		_ IF KillPipeAB THEN [] ELSE level1[a];
level2[b]		_ IF KillPipeAB THEN [] ELSE level2[a];
level3[b]		_ IF KillPipeAB  -- p l s must be preserved for restart
THEN [p:level3[a].p, l:level3[a].l, s:level3[a].s] ELSE level3[a];

lastCycleDelayedBA	_ DelayACycleAB;
level3RejectingBA	_ EPRejectB;
killPipeBA			_ KillPipeAB;
Lev2CondEffectBA	_ level2[b].condOp;
Lev2CondSelBA		_ level2[b].condSel;
Lev3CaddrBA		_ IF level3RejectingBA THEN DragonIFU.noStore ELSE level3[b].c;

IStkPushBA
_ IF level3RejectingBA THEN FALSE ELSE level3[b].iStackOp=push;
IStkPopBA
_ IF level3RejectingBA THEN FALSE ELSE level3[b].iStackOp=pop;
Lev3ITrapEffectBA
_ IF level3RejectingBA THEN none ELSE level3[b].iTrapOp;
Lev3PBA		_ Dragon.LTD[level3[b].p];
Lev3LBA		_ level3[b].l;

FPCSUAluBA	_ IF NOT level3RejectingBA AND level1[b].euPBus=FetchFPAlu
THEN unload ELSE dont;
FPCSUMultBA	_ IF NOT level3RejectingBA AND level1[b].euPBus=FetchFPMult
THEN unload ELSE dont;
FPCSLoadBA		_ IF NOT level3RejectingBA AND
level2[b].euPBus=StoreFP
THEN load ELSE dont;
KBus	_ Dragon.LTD
[(((level1[b].a*LONG[256]) + level1[b].b)*256 + level3[b].c)*256];

EUAluLeftisR1BA	_ level1[b].aluLt=r1;
EUAluLeftisR3BA	_ level1[b].aluLt=r3;

EUAluRightisR1BA	_ level1[b].aluRt=r1;
EUAluRightisR3BA	_ level1[b].aluRt=r3;
EUAluRightisKBA	_ level1[b].aluRt=k;

EUS1isR1BA			_ level1[b].store1=r1;
EUS1isR3BA			_ level1[b].store1=r3;

EUR2isR3BA			_ level2[b].result2=r3;
EUS3isR3BA			_ level2[b].store3=r3;

EUTrapBA			_ level2[b].condOp # microJump;
EUHoldCarryBA		_ killPipeBA;

IF XBSourceBA = pipe3PC THEN XBus _ Dragon.LTD[level3[b].p];
}
ENDCELL


’IPipe.rose
Copyright c 1984 by Xerox Corporation.  All rights reserved.
Uses MicroInstructionBA and microinstruction history to set up EUControl
It interfaces with the IDecoder above and the IStack below
May raise DelayACycleAB
Last edited by: McCreight, April 13, 1984 5:46:06 pm PST 
Last edited by: Curry, August 23, 1984 1:59:55 pm PDT

Decoder
Exceptions
Stack
EU

FP
euPBus PBus

Serial debugging interface

Timing and housekeeping interface
Send off EU PhA Control


PhA KBus and XBus Control
Every microinstruction that causes the EU to drive the KBus must insure that following micros do not conflict.


PhB State changes

Send off PhB Exception Control to IDecoder:
Send off PhB IStack Control and Data:
FP Control
May Need nop load to clock D regs
OR level1[b].euPBus=FetchFPAlu
OR level1[b].euPBus=FetchFPMult

Send off PhB EU Control and Data

Check to see if XBus driven from IPipe during phB
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