[Indigo]<Dragon>IFU>Rosemary>Save>IFU.rose!1

IFU.rose

Last Edited by: Barth, February 8, 1984 10:51 am

Last Edited by: Twilliams, August 28, 1984 9:15:49 am PDT

Last edited by: McCreight, May 3, 1984 9:53:39 am PDT

Last edited by: Curry, August 21, 1984 12:40:12 pm PDT

Signal names obey the following convention: If a signal x is computed during PhA and remains valid throughout the following PhB, it is denoted as xAB. If x is computed during PhA and can change during the following PhB (as, for example, in precharged logic), it is denoted as xA. In this latter case, a client wanting to use x during PhB must receive it in his own latch open during PhA. xBA and xB are defined symmetrically. Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., PNPError for PBus Negative-TRUE Parity Error).

Directory Dragon, DragonIFU, DragonMicroPLA;

Imports Atom;

Library IFetcher, IDecoder, IPipe, IRegAddr, IStack, IFP;

IMisc: CELL [

Serial debugging interface

DHoldAB <BOOL,

Timing and housekeeping interface

PhA <BOOL,

PhB <BOOL,

Serial debugging interface within IFU

DHold0BA >BOOL,

DHold1AB >BOOL

]

EvalSimple

IF PhA THEN {DHold1AB ← DHold0BA};

IF PhB THEN {DHold0BA ← DHoldAB};

ENDCELL;

IFU: CELL [

EU

KBus =INT[32], -- PhA bidirectional, PhB A,B,C to EU

EUAluLeftisR1BA >BOOL, -- Alu Left Default is aRam

EUAluLeftisR3BA >BOOL, -- Alu Left Default is aRam

EUAluRightisR1BA >BOOL, -- Alu Right Default is bRam

EUAluRightisR3BA >BOOL, -- Alu Right Default is bRam

EUAluRightisKBA >BOOL, -- Alu Right Default is bRam

EUAluOpAB >EnumType["Dragon.ALUOps"],

EUCondSelAB >EnumType["Dragon.CondSelects"],

EUTrapBA >BOOL,

EUHoldCarryBA >BOOL,

EUS1isR1BA >BOOL, -- Default is bRam

EUS1isR3BA >BOOL, -- Default is bRam

EUR2isR3BA >BOOL, -- Default is R1

EUS3isR3BA >BOOL, -- Default is S2

EUR3isR2AB >BOOL, -- Default is RData

EUWriteToPBusAB >BOOL,

EUCheckPParityAB >BOOL,

EUConditionBA <BOOL,

FP

FPStatusB <EnumType["DragonFP.Status"],

FPCSLoadBA >EnumType["DragonFP.CSLoad"],

FPCSUAluBA >EnumType["DragonFP.CSUnload"],

FPCSUMultBA >EnumType["DragonFP.CSUnload"],

P Interfaces for EU cache

EPCmdA >EnumType["Dragon.PBusCommands"],

EPRejectB =BOOL, -- driven by IFP

EPFaultB =EnumType["Dragon.PBusFaults"], -- driven by IFP

P Interfaces for IFU cache

IPData =INT[32], -- address PhA, data PhB

IPCmdA >EnumType["Dragon.PBusCommands"],

IPRejectB <BOOL,

IPFaultB <EnumType["Dragon.PBusFaults"],

IPParityB <BOOL,

IPNPErrorB =BOOL,

Serial debugging interface

ResetAB <BOOL,

DHoldAB <BOOL,

DShiftAB <BOOL,

DExecuteAB <BOOL,

DNSelectAB <BOOL,

DDataInAB <BOOL,

DDataOutAB =BOOL,

Timing and housekeeping interface

RescheduleAB <BOOL,

PhA <BOOL,

PhB <BOOL,

Fake interface for simulation

InstrCountAB >INT[32]

]

Expand

XBus :INT[32],

DHold0BA :BOOL;

DHold1AB :BOOL;

IFetcher <-> IDecoder

PreOpA :INT[8];

PreAlphaA :INT[8];

PreBetaA :INT[8];

PreGammaA :INT[8];

PreDeltaA :INT[8];

PreLengthAB :INT[3] ← "1"; -- prevents BoundsFault at startup

InstReadyAB :BOOL;

PreFetchFaultedBA :BOOL; -- latched until JumpB

GetNextInstB :BOOL;

JumpB :BOOL;

IDecoder <-> IRegAddr

ASum0B :EnumType["DragonMicroPLA.ABRegSum0"];

ASum1B :EnumType["DragonMicroPLA.ABRegSum1"];

BSum0B :EnumType["DragonMicroPLA.ABRegSum0"];

BSum1B :EnumType["DragonMicroPLA.ABRegSum1"];

CSum0A :EnumType["DragonMicroPLA.CRegSum0"];

CSum1A :EnumType["DragonMicroPLA.CRegSum1"];

LSum0A :EnumType["DragonMicroPLA.LSource0"];

LSum1A :EnumType["DragonMicroPLA.LSource1"];

SSum0A :EnumType["DragonMicroPLA.SSource0"];

SSum1A :EnumType["DragonMicroPLA.SSource1"];

DeltaSPlus2A :INT[2];

OpBA :INT[8];

AlphaBA :INT[8];

BetaBA :INT[8];

ReadSLimitA :BOOL;

SetSLimitA :BOOL;

LAB :INT[7];

SAB :INT[7];

EStkOverflowBA :BOOL;

IDecoder <-> IPipe

Lev0PA :INT[32];

Lev0LA :INT[8];

Lev0SA :INT[8];

Lev0AaddrBA :INT[8];

Lev0BaddrBA :INT[8];

Lev0CaddrA :INT[8];

Lev0AluRtIsKBA :BOOL;

Lev0AluOpBA :EnumType["Dragon.ALUOps"];

Lev0CondSelBA :EnumType["Dragon.CondSelects"];

Lev0CondEffectBA :EnumType["DragonMicroPLA.CondEffect"];

Lev0IStackPostEffectBA :EnumType["DragonMicroPLA.IStackPostEffect"];

Lev0ITrapPostEffectBA :EnumType["DragonMicroPLA.ITrapPostEffect"];

Lev0EuPBusCmdBA :EnumType["Dragon.PBusCommands"];

Lev2CondSelBA :EnumType["Dragon.CondSelects"];

Lev3CaddrBA :INT[8];

XBSourceBA :EnumType["DragonMicroPLA.XBSource"];

DontBypassBA :BOOL;

KillPipeAB :BOOL;

PushPendingAB :BOOL;

PopPendingAB :BOOL;

ITrapEffectPendingAB :EnumType["DragonMicroPLA.ITrapPostEffect"];

Lev3ITrapEffectBA :EnumType["DragonMicroPLA.ITrapPostEffect"];

DelayACycleAB :BOOL;

Lev2CondEffectBA :EnumType["DragonMicroPLA.CondEffect"];

Stack I/O with IDecoder and IPipe

PushLevel3BA :BOOL;

IStkPushBA :BOOL;

IStkPopBA :BOOL;

IStkEmptyA :BOOL;

IStkTooFullA :BOOL;

Lev3PBA :INT[32];

Lev3LBA :INT[8];

fetcher: IFetcher[];

decoder: IDecoder[

PreLengthA: PreLengthAB,

InstReadyA: InstReadyAB ]
init NARROW[initData, Atom.PropList].GetPropFromList[$decoder] |;

aReg: IALRegAddr[] init NARROW[NARROW[initData, Atom.PropList].GetPropFromList[$aReg], Atom.PropList].PutPropOnList[$xBusPos, NEW[INT ← 32-0-7]] |;

bReg: IBSRegAddr[] init NARROW[NARROW[initData, Atom.PropList].GetPropFromList[$bReg], Atom.PropList].PutPropOnList[$xBusPos, NEW[INT ← 32-8-7]] |;

cReg: ICRegAddr[];

pipe: IPipe[];

stack: IStack[];

ifp: IFP[];

misc: IMisc[]

ENDCELL