DragonMicroPLA:
CEDAR
DEFINITIONS =
BEGIN
MaxPLAMinterms: INT = 800;
PLAMinterms: [0..MaxPLAMinterms);
PLAType: TYPE ~ ARRAY [ 0..MaxPLAMinterms) OF PlaRow;
PLA: READONLY REF PLAType;
opCodeMap: PACKED ARRAY [0..256) OF BOOLEAN;
PlaRow: TYPE = RECORD [ andRow: AndRow, orRow: OrRow];
AndRow: TYPE = RECORD [ sigPhBArgs: SigPhBArgs, phBArgs: PhBArgs];
OrRow: TYPE = RECORD [ m: MicroInst];
PhBArgs:
TYPE = RECORD [
state :IFUState,
op :DragOpsCross.Inst,
alpha :Dragon.HexByte,
beta :Dragon.HexByte,
delayACycle :BOOL, -- from pipeline interlocks or EU reject
iStkEmpty :BOOL,
pushPending :BOOL ← FALSE,
popPending :BOOL ← FALSE,
instReady :BOOL ];
BoolFalse: TYPE = BOOLEAN ← FALSE;
SigPhBArgs:
TYPE =
RECORD [
state :SigIFUState,
beta :SigInstByte,
alpha :SigInstByte,
op :SigInstByte,
delayACycle :BOOL,
iStkEmpty :BOOL,
pushPending :BOOL,
popPending :BOOL,
instReady :BOOL];
SigPhBArgsTrue: SigPhBArgs = [
state :SigIFUStateTrue,
beta :SigInstByteTrue,
alpha :SigInstByteTrue,
op :SigInstByteTrue,
delayACycle :TRUE,
iStkEmpty :TRUE,
pushPending :TRUE,
popPending :TRUE,
instReady :TRUE];
SigPhBArgsFalse: SigPhBArgs = [
state :SigIFUStateFalse,
beta :SigInstByteFalse,
alpha :SigInstByteFalse,
op :SigInstByteFalse,
delayACycle :FALSE,
iStkEmpty :FALSE,
pushPending :FALSE,
popPending :FALSE,
instReady :FALSE];
SigInstByte:
TYPE =
RECORD [
bit0 :BOOL,
bit1 :BOOL,
bit2 :BOOL,
bit3 :BOOL,
bit4 :BOOL,
bit5 :BOOL,
bit6 :BOOL,
bit7 :BOOL];
SigInstByteTrue: SigInstByte = [
bit0 :TRUE,
bit1 :TRUE,
bit2 :TRUE,
bit3 :TRUE,
bit4 :TRUE,
bit5 :TRUE,
bit6 :TRUE,
bit7 :TRUE];
SigInstByteFalse: SigInstByte = [
bit0 :FALSE,
bit1 :FALSE,
bit2 :FALSE,
bit3 :FALSE,
bit4 :FALSE,
bit5 :FALSE,
bit6 :FALSE,
bit7 :FALSE];
PhAArgs:
TYPE = RECORD [
state :IFUState,
ifuStatusControl :IFUStatusControl,
iTrapEffect3 :ITrapPostEffect ← none,
delayed :BOOL ← FALSE,
done :BOOL ← FALSE,
reset :BOOL ← FALSE,
reschedule :BOOL ← FALSE,
preFetchFaulted :BOOL ← FALSE, -- from IFetcher
pushPending :BOOL ← FALSE,
popPending :BOOL ← FALSE,
iTrapEffectPending :ITrapPostEffect ← none,
iStkOverflow :BOOL ← FALSE,
eStkOverflow :BOOL ← FALSE, -- from IFU
aluCondResult2 :BOOL ← FALSE, -- input pin from EU
aluCond2 :Dragon.CondSelects ← False, -- from IFU pipeline
condEffect2 :CondEffect ← macroTrap, -- from IFU pipeline
pBusReject3 :BOOL,
pBusFault3 :Dragon.PBusFaults ← None ];
Exceptions:
TYPE =
MACHINE
DEPENDENT {
none, reserve1, aboutToReset, reset,
epFault, euCC, epReject, cJump,
rschlWait, iStkOFlow, eStkOFlow, iFtchFault,
reserve12, reserve13, reserve14, reserve15};
CondEffect: TYPE = MACHINE DEPENDENT {macroTrap(0), macroJump, microJump};
IStackPostEffect: TYPE = MACHINE DEPENDENT {none(0), push, pop};
ITrapPostEffect: TYPE = MACHINE DEPENDENT {none(0), enable, disable};
XBSource:
TYPE =
MACHINE
DEPENDENT {
pcPlusLen(0), pcPlusXA, pcPlusAlphaS, pcPlusBetaAlphaS,
pc, xA, reserve6, deltaGammaBetaAlpha,
xopGenerator, trapPCGenerator, reserve10, reserve11,
iStackPC, pipe3PC, reserve14, reserve15};
PipedPLSASpec: TYPE = MACHINE DEPENDENT {pls(0), pLenLSnext, pAlphasLSnext};
XASource:
TYPE =
MACHINE
DEPENDENT {
none(0), bAddrIFUReg, reserve2, reserve3, -- Both essentially none
alpha, beta, betaAlpha, deltaGammaBetaAlpha,
fpLdAMsw, fpLdALsw, fpUnldMsw, fpUnldLsw,
fpLdBMsw, fpLdBLsw, reserve14, fpLdMode};
DeltaSab: TYPE = MACHINE DEPENDENT { zero(0), pop(1) };
DeltaSc: TYPE = MACHINE DEPENDENT { zero(0), push(1) };
ABReg: TYPE = RECORD [ s0: ABRegSum0, s1: ABRegSum1 ]; -- 7 bits
ABRegSum0: TYPE = MACHINE DEPENDENT {cBase(0), aBase, s, l, iRef, zero};
ABRegSum1:
TYPE =
MACHINE
DEPENDENT {
zero(0), one(1), two(2), three(3),
minus4(4), minus3(5), minus2(6), minus1(7),
op47(8), alpha(9), alpha03(10), alpha47(11),
deltaS(12), beta(13), beta03(14), beta47(15)};
CReg: TYPE = RECORD [ s0: CRegSum0, s1: CRegSum1 ]; -- 7 bits
CRegSum0: TYPE = MACHINE DEPENDENT {aBase(0), cBase, l, s, zero, iRef};
CRegSum1:
TYPE =
MACHINE
DEPENDENT {
-- address bit 1 inverted from ABRegSum1
minus4(0), minus3(1), minus2(2), minus1(3),
zero(4), one(5), two(6), three(7),
deltaS(8), beta(9), beta03(10), beta47(11),
op47(12), alpha(13), alpha03(14), alpha47(15)};
LSource: TYPE = RECORD [ s0: LSource0, s1: LSource1 ]; -- 4 bits
LSource0: TYPE = MACHINE DEPENDENT {l(0), s, zero, xBus};
LSource1: TYPE = MACHINE DEPENDENT { zero(0), one, alpha};
SSource: TYPE = RECORD [ s0: SSource0, s1: SSource1 ]; -- 4 bits
SSource0: TYPE = MACHINE DEPENDENT {s(0), l, xBus, zero};
SSource1: TYPE = MACHINE DEPENDENT { deltaS(0), alpha, zero, one};
These must agree with DragOpsCross.ProcessorRegister
abStackTop: ABReg = [ s , zero ];
cStackTop: CReg = [ s , zero ];
constantZero: ABReg = [ cBase , zero ];
euField: CReg = [ aBase , minus1 ];
inhibitStore: CReg = [ aBase , minus4 ];
euGF: ABReg = [ aBase , zero ];
ifuXBus: CReg = [ iRef , minus4 ];
ifuLevel3LS: ABReg = [ iRef , minus3 ];
ifuYoungestL: ABReg = [ iRef , minus2 ];
IFUState:
TYPE =
RECORD [
cycle: [0..64) ← 0,
rescheduleWaiting: BOOL ← FALSE, -- goes into trap PC generator
inhibitTraps: BOOL ← FALSE, -- disables reschedule and stack overflows
exceptions: Exceptions -- prioritized phase A exceptions
];
SigIFUState must be in the same order as IFUState for the AMTypes stuff in Puff to work
SigIFUState:
TYPE =
RECORD [
cycle: BOOL ← TRUE,
rescheduleWaiting: BOOL ← TRUE,
inhibitTraps: BOOL ← TRUE,
exceptions: BOOL ← TRUE];
SigIFUStateTrue: SigIFUState = [
cycle :TRUE,
rescheduleWaiting :TRUE,
inhibitTraps :TRUE,
exceptions :TRUE];
SigIFUStateFalse: SigIFUState = [
cycle :FALSE,
rescheduleWaiting :FALSE,
inhibitTraps :FALSE,
exceptions :FALSE];
IFUStatusControl:
TYPE =
RECORD [
reschedule: BitCont ← nop,
inhibit: BitCont ← nop -- prioritized phase A exceptions
];
BitCont: TYPE = {nop, clear, set};
Calculated during phA for use during phB.
MicroTrap:
TYPE =
RECORD [
trapPC: Dragon.HexWord ← 0,
killPipe: BOOL ← FALSE
];
Calculated during phB.
MicroInst:
TYPE =
RECORD [
Needed during the first PhB of the macro. Must be fast. May be unary.
aReg, bReg: ABReg ← constantZero,
dontGetNextMacro: BOOL ← FALSE, -- FALSE for last micro of sequential macro
xBSource: XBSource ← pcPlusLen,
doMacroJump:
BOOL ←
FALSE,
TRUE for some micro of jmps, calls, returns, & jmping Cjmps
Needed during the following PhA.
cReg: CReg ← inhibitStore,
lSource: LSource ← [ l, zero ],
sSource: SSource ← [ s, deltaS ],
deltaSa: DeltaSab ← zero,
deltaSb: DeltaSab ← zero,
deltaSc: DeltaSc ← zero,
xASource: XASource ← none,
aluRtIsK: BOOL ← FALSE, -- True for Wt and many others
aluOp: Dragon.ALUOps ← Or,
condSel: Dragon.CondSelects ← False,
condEffect: CondEffect ← macroTrap,
dontBypass: BOOL ← FALSE, -- TRUE for EXCH
iStackPostEffect: IStackPostEffect ← none,
iTrapPostEffect: ITrapPostEffect ← none,
euPBusCmd: Dragon.PBusCommands ← NoOp,
pipedPLSASpec: PipedPLSASpec ← pls,
pushLevel3: BOOL ← FALSE,
delayed: BOOL ← FALSE
];
DefaultMicro, BlankMicro: MicroInst = [];
NoOpMicro: MicroInst = [ dontGetNextMacro: TRUE, xBSource: pc ];
GetMicroInst: PROC [bArgs: PhBArgs] RETURNS [ m: MicroInst];
GetMicroTrap: PROC [aArgs: PhAArgs] RETURNS [ m: MicroTrap, newState: IFUState];
AddPLARow: PROC [sigPhBArgs: SigPhBArgs, phBArgs: PhBArgs, m: MicroInst];
FPAddPLARow: PROC[ fpOpType: DragonFP.FPOpType, sigPhBArgs: SigPhBArgs, phBArgs: PhBArgs, m: MicroInst];
GeneratePLA: PROC;
END.