DIRECTORY
RoseTypes, IFUFetch, RoseCreate, DragOpsCross, BitOps, DragonRosemary, DragonRoseExtras, IFUPLAFetchControl, IFUPLAFetchPreDecode, Dragon, SwitchTypes, EnumTypes, NumTypes;

IFUFetchImpl: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, DragonRosemary, DragonRoseExtras, IFUPLAFetchControl, IFUPLAFetchPreDecode, EnumTypes, NumTypes
EXPORTS IFUFetch

= BEGIN OPEN
RoseTypes, IFUFetch;

PBusCommands: TYPE = Dragon.PBusCommands;
PBusFaults: TYPE = Dragon.PBusFaults;
WtIndexCtl: TYPE = IFUPLAFetchControl.WtIndexCtl;
JumpOffsetSel: TYPE = IFUPLAFetchPreDecode.JumpOffsetSel;


RegisterCells: PROC =
BEGIN
FetchControl _ RoseCreate.RegisterCellType[name: "FetchControl",
expandProc: NIL,
ioCreator: CreateFetchControlIO, driveCreator: CreateFetchControlDrive, initializer: InitializeFetchControl,
evals: [EvalSimple: FetchControlEvalSimple],
tests: LIST[],
ports: CreateFetchControlPorts[]
];
FetchIndexing _ RoseCreate.RegisterCellType[name: "FetchIndexing",
expandProc: NIL,
ioCreator: CreateFetchIndexingIO, driveCreator: CreateFetchIndexingDrive, initializer: InitializeFetchIndexing,
evals: [EvalSimple: FetchIndexingEvalSimple],
tests: LIST[],
ports: CreateFetchIndexingPorts[]
];
FetchPreDecode _ RoseCreate.RegisterCellType[name: "FetchPreDecode",
expandProc: NIL,
ioCreator: CreateFetchPreDecodeIO, driveCreator: CreateFetchPreDecodeDrive, 
evals: [EvalSimple: FetchPreDecodeEvalSimple],
tests: LIST[],
ports: CreateFetchPreDecodePorts[]
];
FetchAddr _ RoseCreate.RegisterCellType[name: "FetchAddr",
expandProc: NIL,
ioCreator: CreateFetchAddrIO, driveCreator: CreateFetchAddrDrive, initializer: InitializeFetchAddr,
evals: [EvalSimple: FetchAddrEvalSimple],
tests: LIST[],
ports: CreateFetchAddrPorts[]
];
FetchBuffer _ RoseCreate.RegisterCellType[name: "FetchBuffer",
expandProc: NIL,
ioCreator: CreateFetchBufferIO, driveCreator: CreateFetchBufferDrive, initializer: InitializeFetchBuffer,
evals: [EvalSimple: FetchBufferEvalSimple],
tests: LIST[],
ports: CreateFetchBufferPorts[]
];
Fetch _ RoseCreate.RegisterCellType[name: "Fetch",
expandProc: FetchExpand,
ioCreator: CreateFetchIO, driveCreator: CreateFetchDrive, 
evals: [],
tests: LIST[],
ports: CreateFetchPorts[]
];
END;
otherss: SymbolTable _ RoseCreate.GetOtherss["IFUFetch.partsAssertions"];
FetchControl: PUBLIC CellType;

CreateFetchControlPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUFetch.FetchControl.rosePorts"]};

FetchControlSwitchIORef: TYPE = REF FetchControlSwitchIORec;
FetchControlSwitchIORec: TYPE = RECORD [
IPCmnd3A: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,IPRejectB: SwitchTypes.SwitchVal
,IPFaultB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,MacroJumpBA: SwitchTypes.SwitchVal
,IPFaulted0BA: SwitchTypes.SwitchVal
,IncrPFetchAddrBA: SwitchTypes.SwitchVal
,ResetBA: SwitchTypes.SwitchVal
,BufBytesOccM1A: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,FetchWtB: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,FetchingAB: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

FetchControlSimpleIORef: TYPE = REF FetchControlSimpleIORec;
FetchControlSimpleIORec: TYPE = RECORD [
fill0: [0 .. 255],
IPCmnd3A: PBusCommands
,fill1: [0 .. 32767],
IPRejectB: BOOLEAN
,fill2: [0 .. 4095],
IPFaultB: PBusFaults
,fill3: [0 .. 32767],
MacroJumpBA: BOOLEAN
,fill4: [0 .. 32767],
IPFaulted0BA: BOOLEAN
,fill5: [0 .. 32767],
IncrPFetchAddrBA: BOOLEAN
,fill6: [0 .. 32767],
ResetBA: BOOLEAN
,fill7: [0 .. 2047],
BufBytesOccM1A: [0..31]
,fill8: [0 .. 8191],
FetchWtB: WtIndexCtl
,fill9: [0 .. 32767],
FetchingAB: BOOLEAN
,fill10: [0 .. 32767],
PhA: BOOLEAN
,fill11: [0 .. 32767],
PhB: BOOLEAN
];

FetchControlDriveRef: TYPE = REF FetchControlDriveRec;
FetchControlDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY FetchControlPort OF DriveLevel];
FetchControlPort: TYPE = {
IPCmnd3A, IPRejectB, IPFaultB, MacroJumpBA, IPFaulted0BA, IncrPFetchAddrBA, ResetBA, BufBytesOccM1A, FetchWtB, FetchingAB, PhA, PhB};

CreateFetchControlIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[FetchControlSwitchIORec] ELSE NEW[FetchControlSimpleIORec];
};

CreateFetchControlDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[FetchControlDriveRec];
};

FetchControlStateRef: TYPE = REF FetchControlStateRec;
FetchControlStateRec: TYPE = RECORD [
jumpPendingAB,	jumpPendingBA:	BOOL,
newFetchBA:								BOOL,
fetchingBA:									BOOL,
faultedAB:									BOOL,
bufBytesOccM1AB:								[0..32)

];

InitializeFetchControl: Initializer = {
state: FetchControlStateRef _ NEW[FetchControlStateRec];
cell.realCellStuff.state _ state;
};

FetchControlEvalSimple: SimpleEval =
BEGIN
drive: FetchControlDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: FetchControlSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: FetchControlSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: FetchControlStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
IF PhA THEN {
jumpPendingAB		_ jumpPendingBA;
faultedAB			_ IPFaulted0BA;
FetchingAB			_ fetchingBA;
bufBytesOccM1AB _ BufBytesOccM1A;
IPCmnd3A	_ IF newFetchBA THEN Fetch ELSE NoOp};
IF PhB THEN {
[ [
jumpPending:		jumpPendingBA,
newFetch:			newFetchBA,
fetching:				fetchingBA,
faulted:				IPFaulted0BA,
wtIndexCtl:			FetchWtB
] ] _ IFUPLAFetchControl.FetchControlProc[ [	-- Static Logic
jump:					MacroJumpBA,
getNext:				FALSE, -- not used, formerly GetNextInstBA
reset:					ResetBA,
reject:					IPRejectB,
jumpPending:		jumpPendingAB,
fetching:				FetchingAB,
bytesOccM1:			bufBytesOccM1AB,
faulted:				faultedAB,
ipPageFault:			IPFaultB=page
] ];
IncrPFetchAddrBA _ newFetchBA };

END;
END;
FetchIndexing: PUBLIC CellType;

CreateFetchIndexingPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUFetch.FetchIndexing.rosePorts"]};

FetchIndexingSwitchIORef: TYPE = REF FetchIndexingSwitchIORec;
FetchIndexingSwitchIORec: TYPE = RECORD [
FetchWtB: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,FetchingAB: SwitchTypes.SwitchVal
,PCBusB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,OpLengthAB: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,GetNextInstBA: SwitchTypes.SwitchVal
,MacroJumpBA: SwitchTypes.SwitchVal
,IBufWrtWdBc: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,IBufRdByteAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,BufBytesOccM1A: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

FetchIndexingSimpleIORef: TYPE = REF FetchIndexingSimpleIORec;
FetchIndexingSimpleIORec: TYPE = RECORD [
fill0: [0 .. 8191],
FetchWtB: WtIndexCtl
,fill1: [0 .. 32767],
FetchingAB: BOOLEAN
,PCBusB: ARRAY [0..2) OF CARDINAL
,fill3: [0 .. 8191],
OpLengthAB: [0..7]
,fill4: [0 .. 32767],
GetNextInstBA: BOOLEAN
,fill5: [0 .. 32767],
MacroJumpBA: BOOLEAN
,fill6: [0 .. 4095],
IBufWrtWdBc: [0..15]
,IBufRdByteAc: CARDINAL
,fill8: [0 .. 2047],
BufBytesOccM1A: [0..31]
,fill9: [0 .. 32767],
PhA: BOOLEAN
,fill10: [0 .. 32767],
PhB: BOOLEAN
];

FetchIndexingDriveRef: TYPE = REF FetchIndexingDriveRec;
FetchIndexingDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY FetchIndexingPort OF DriveLevel];
FetchIndexingPort: TYPE = {
FetchWtB, FetchingAB, PCBusB, OpLengthAB, GetNextInstBA, MacroJumpBA, IBufWrtWdBc, IBufRdByteAc, BufBytesOccM1A, PhA, PhB, FetchIndexingPortTypePad11};

CreateFetchIndexingIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[FetchIndexingSwitchIORec] ELSE NEW[FetchIndexingSimpleIORec];
};

CreateFetchIndexingDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[FetchIndexingDriveRec];
};

FetchIndexingStateRef: TYPE = REF FetchIndexingStateRec;
FetchIndexingStateRec: TYPE = RECORD [
wtAB,	wtBA:	[0..8),
rdAB,		rdBA:	[0..32)

];

InitializeFetchIndexing: Initializer = {
state: FetchIndexingStateRef _ NEW[FetchIndexingStateRec];
cell.realCellStuff.state _ state;
};

FetchIndexingEvalSimple: SimpleEval =
BEGIN
drive: FetchIndexingDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: FetchIndexingSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: FetchIndexingSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: FetchIndexingStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
IF PhA
THEN {
wtAB		_ wtBA;
rdAB		_ rdBA;
IBufRdByteAc _ BitOps.IBIW[TRUE, 0, 16, rdBA MOD 16] }
ELSE  IBufRdByteAc _ 0;
IF PhB
THEN {
SELECT FetchWtB FROM
clear	=> wtBA _ 0;
hold	=> wtBA _ wtAB;
inc	=> wtBA _ (wtAB+1) MOD 8;
ENDCASE			=> DragonRosemary.Assert[FALSE, "Hello?"];

rdBA _ (SELECT TRUE FROM
MacroJumpBA => (DragonRoseExtras.LFD[PCBusB] MOD DragOpsCross.bytesPerWord),
GetNextInstBA => (rdAB+OpLengthAB) MOD 32,
ENDCASE => rdAB);

IF FetchingAB
THEN	IBufWrtWdBc _ BitOps.IBIW[TRUE, 0, 4, wtAB MOD 4]
ELSE	IBufWrtWdBc _ 0;
}
ELSE IBufWrtWdBc _ 0;

BufBytesOccM1A _ (4*wtBA-rdBA-1+64) MOD 32;
END;
END;
FetchPreDecode: PUBLIC CellType;

CreateFetchPreDecodePorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUFetch.FetchPreDecode.rosePorts"]};

FetchPreDecodeSwitchIORef: TYPE = REF FetchPreDecodeSwitchIORec;
FetchPreDecodeSwitchIORec: TYPE = RECORD [
OpAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BufBytesOccM1A: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,OpLengthAB: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,JumpOffsetSelAB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,OpLengthBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,InstReadyAB: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

FetchPreDecodeSimpleIORef: TYPE = REF FetchPreDecodeSimpleIORec;
FetchPreDecodeSimpleIORec: TYPE = RECORD [
fill0: [0 .. 255],
OpAB: [0..255]
,fill1: [0 .. 2047],
BufBytesOccM1A: [0..31]
,fill2: [0 .. 8191],
OpLengthAB: [0..7]
,fill3: [0 .. 4095],
JumpOffsetSelAB: JumpOffsetSel
,fill4: [0 .. 8191],
OpLengthBA: [0..7]
,fill5: [0 .. 32767],
InstReadyAB: BOOLEAN
,fill6: [0 .. 32767],
PhA: BOOLEAN
,fill7: [0 .. 32767],
PhB: BOOLEAN
];

FetchPreDecodeDriveRef: TYPE = REF FetchPreDecodeDriveRec;
FetchPreDecodeDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY FetchPreDecodePort OF DriveLevel];
FetchPreDecodePort: TYPE = {
OpAB, BufBytesOccM1A, OpLengthAB, JumpOffsetSelAB, OpLengthBA, InstReadyAB, PhA, PhB};

CreateFetchPreDecodeIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[FetchPreDecodeSwitchIORec] ELSE NEW[FetchPreDecodeSimpleIORec];
};

CreateFetchPreDecodeDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[FetchPreDecodeDriveRec];
};

FetchPreDecodeEvalSimple: SimpleEval =
BEGIN
drive: FetchPreDecodeDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: FetchPreDecodeSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: FetchPreDecodeSimpleIORef _ NARROW[cell.realCellStuff.newIO];
BEGIN OPEN drive, newIO;
IF PhA THEN {
notInstReady: BOOL;
[ [
opLength:		OpLengthAB,
jumpOffset:		JumpOffsetSelAB,
notInstReady:	notInstReady
] ]
_ IFUPLAFetchPreDecode.FetchPreDecodeProc[ [	-- Static logic
preOp:	LOOPHOLE[OpAB],
bytesOccM1:	BufBytesOccM1A
] ];
IF DragonRosemary.OpLength[OpAB]#OpLengthAB THEN DragonRosemary.Assert[FALSE,
"DragonImpl.OpLength # IFUPLAFetchPreDecode.GenFetchPreDecodePLA"];
InstReadyAB _ NOT notInstReady };
IF PhB THEN OpLengthBA _ OpLengthAB;

END;
END;
FetchAddr: PUBLIC CellType;

CreateFetchAddrPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUFetch.FetchAddr.rosePorts"]};

FetchAddrSwitchIORef: TYPE = REF FetchAddrSwitchIORec;
FetchAddrSwitchIORec: TYPE = RECORD [
IPData: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCBusB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,MacroJumpBA: SwitchTypes.SwitchVal
,IncrPFetchAddrBA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

FetchAddrSimpleIORef: TYPE = REF FetchAddrSimpleIORec;
FetchAddrSimpleIORec: TYPE = RECORD [
IPData: ARRAY [0..2) OF CARDINAL
,PCBusB: ARRAY [0..2) OF CARDINAL
,fill2: [0 .. 32767],
MacroJumpBA: BOOLEAN
,fill3: [0 .. 32767],
IncrPFetchAddrBA: BOOLEAN
,fill4: [0 .. 32767],
PhA: BOOLEAN
,fill5: [0 .. 32767],
PhB: BOOLEAN
];

FetchAddrDriveRef: TYPE = REF FetchAddrDriveRec;
FetchAddrDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY FetchAddrPort OF DriveLevel];
FetchAddrPort: TYPE = {
IPData, PCBusB, MacroJumpBA, IncrPFetchAddrBA, PhA, PhB, FetchAddrPortTypePad6, FetchAddrPortTypePad7};

CreateFetchAddrIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[FetchAddrSwitchIORec] ELSE NEW[FetchAddrSimpleIORec];
};

CreateFetchAddrDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[FetchAddrDriveRec];
};

FetchAddrStateRef: TYPE = REF FetchAddrStateRec;
FetchAddrStateRec: TYPE = RECORD [
errorAB:				BOOL,                         --not used !!! JH
fetchAddrBA:		Dragon.HexWord,
fetchAddrAB:		Dragon.HexWord

];

InitializeFetchAddr: Initializer = {
state: FetchAddrStateRef _ NEW[FetchAddrStateRec];
cell.realCellStuff.state _ state;
};

FetchAddrEvalSimple: SimpleEval =
BEGIN
drive: FetchAddrDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: FetchAddrSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: FetchAddrSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: FetchAddrStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;

drive[IPData] _ IF PhA THEN drive ELSE ignore;

IF PhA THEN {
IPData _ DragonRoseExtras.LTD[fetchAddrBA/4];		-- Byte to word happens here
IF IncrPFetchAddrBA
THEN	fetchAddrAB _ fetchAddrBA+4	-- byte offset in loc 30,31
ELSE	fetchAddrAB _ fetchAddrBA };
IF PhB THEN {
IF MacroJumpBA
THEN	fetchAddrBA _ DragonRoseExtras.LFD[PCBusB]
ELSE	fetchAddrBA _ fetchAddrAB };
END;
END;
FetchBuffer: PUBLIC CellType;

CreateFetchBufferPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUFetch.FetchBuffer.rosePorts"]};

FetchBufferSwitchIORef: TYPE = REF FetchBufferSwitchIORec;
FetchBufferSwitchIORec: TYPE = RECORD [
IPData: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,IBufWrtWdBc: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,IBufRdByteAc: PACKED ARRAY [0 .. 16) OF SwitchTypes.SwitchVal
,OpAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,AlphaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BetaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,GammaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DeltaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

FetchBufferSimpleIORef: TYPE = REF FetchBufferSimpleIORec;
FetchBufferSimpleIORec: TYPE = RECORD [
IPData: ARRAY [0..2) OF CARDINAL
,fill1: [0 .. 4095],
IBufWrtWdBc: [0..15]
,IBufRdByteAc: CARDINAL
,fill3: [0 .. 255],
OpAB: [0..255]
,fill4: [0 .. 255],
AlphaAB: [0..255]
,fill5: [0 .. 255],
BetaAB: [0..255]
,fill6: [0 .. 255],
GammaAB: [0..255]
,fill7: [0 .. 255],
DeltaAB: [0..255]
,fill8: [0 .. 32767],
PhA: BOOLEAN
,fill9: [0 .. 32767],
PhB: BOOLEAN
];

FetchBufferDriveRef: TYPE = REF FetchBufferDriveRec;
FetchBufferDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY FetchBufferPort OF DriveLevel];
FetchBufferPort: TYPE = {
IPData, IBufWrtWdBc, IBufRdByteAc, OpAB, AlphaAB, BetaAB, GammaAB, DeltaAB, PhA, PhB, FetchBufferPortTypePad10, FetchBufferPortTypePad11};

CreateFetchBufferIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[FetchBufferSwitchIORec] ELSE NEW[FetchBufferSimpleIORec];
};

CreateFetchBufferDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[FetchBufferDriveRec];
};

FetchBufferStateRef: TYPE = REF FetchBufferStateRec;
FetchBufferStateRec: TYPE = RECORD [
preOpA:		Dragon.HexByte,
preAlphaA:	Dragon.HexByte,
preBetaA:		Dragon.HexByte,
preGammaA:	Dragon.HexByte,
preDeltaA:	Dragon.HexByte,
iBuf:			ARRAY [0..16) OF Dragon.HexByte

];

InitializeFetchBuffer: Initializer = {
state: FetchBufferStateRef _ NEW[FetchBufferStateRec];
cell.realCellStuff.state _ state;
};

FetchBufferEvalSimple: SimpleEval =
BEGIN
drive: FetchBufferDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: FetchBufferSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: FetchBufferSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: FetchBufferStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
FOR j: [0..4) IN [0..4) DO
IF BitOps.EBFW[IBufWrtWdBc, 4, j] THEN
FOR k: NAT IN [0..4) DO
iBuf[4*j+k] _ BitOps.ECFD[IPData, 32, 8*k, 8];
ENDLOOP;
ENDLOOP;

FOR j: [0..16) IN [0..16) DO
IF BitOps.EBFW[IBufRdByteAc, 16, j] THEN {
preOpA		_ BitOps.WAND[preOpA,		iBuf[j]];
preAlphaA	_ BitOps.WAND[preAlphaA,	iBuf[(j+1) MOD 16]];
preBetaA		_ BitOps.WAND[preBetaA,		iBuf[(j+2) MOD 16]];
preGammaA	_ BitOps.WAND[preGammaA,	iBuf[(j+3) MOD 16]];
preDeltaA	_ BitOps.WAND[preDeltaA,		iBuf[(j+4) MOD 16]] };
ENDLOOP;

IF PhA THEN {
OpAB			_ preOpA;
AlphaAB		_ preAlphaA;
BetaAB		_ preBetaA;
GammaAB	_ preGammaA;
DeltaAB		_ preDeltaA };

IF PhB THEN {
preOpA		_ 255;
preAlphaA	_ 255;
preBetaA		_ 255;
preGammaA	_ 255;
preDeltaA	_ 255 };
END;
END;
Fetch: PUBLIC CellType;

CreateFetchPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUFetch.Fetch.rosePorts"]};

FetchSwitchIORef: TYPE = REF FetchSwitchIORec;
FetchSwitchIORec: TYPE = RECORD [
IPCmnd3A: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,IPRejectB: SwitchTypes.SwitchVal
,IPFaultB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,IPData: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCBusB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,MacroJumpBA: SwitchTypes.SwitchVal
,GetNextInstBA: SwitchTypes.SwitchVal
,ResetBA: SwitchTypes.SwitchVal
,IPFaulted0BA: SwitchTypes.SwitchVal
,OpLengthBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,JumpOffsetSelAB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,InstReadyAB: SwitchTypes.SwitchVal
,OpAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,AlphaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BetaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,GammaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DeltaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

FetchSimpleIORef: TYPE = REF FetchSimpleIORec;
FetchSimpleIORec: TYPE = RECORD [
fill0: [0 .. 255],
IPCmnd3A: PBusCommands
,fill1: [0 .. 32767],
IPRejectB: BOOLEAN
,fill2: [0 .. 4095],
IPFaultB: PBusFaults
,IPData: ARRAY [0..2) OF CARDINAL
,PCBusB: ARRAY [0..2) OF CARDINAL
,fill5: [0 .. 32767],
MacroJumpBA: BOOLEAN
,fill6: [0 .. 32767],
GetNextInstBA: BOOLEAN
,fill7: [0 .. 32767],
ResetBA: BOOLEAN
,fill8: [0 .. 32767],
IPFaulted0BA: BOOLEAN
,fill9: [0 .. 8191],
OpLengthBA: [0..7]
,fill10: [0 .. 4095],
JumpOffsetSelAB: JumpOffsetSel
,fill11: [0 .. 32767],
InstReadyAB: BOOLEAN
,fill12: [0 .. 255],
OpAB: [0..255]
,fill13: [0 .. 255],
AlphaAB: [0..255]
,fill14: [0 .. 255],
BetaAB: [0..255]
,fill15: [0 .. 255],
GammaAB: [0..255]
,fill16: [0 .. 255],
DeltaAB: [0..255]
,fill17: [0 .. 32767],
PhA: BOOLEAN
,fill18: [0 .. 32767],
PhB: BOOLEAN
];

FetchDriveRef: TYPE = REF FetchDriveRec;
FetchDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY FetchPort OF DriveLevel];
FetchPort: TYPE = {
IPCmnd3A, IPRejectB, IPFaultB, IPData, PCBusB, MacroJumpBA, GetNextInstBA, ResetBA, IPFaulted0BA, OpLengthBA, JumpOffsetSelAB, InstReadyAB, OpAB, AlphaAB, BetaAB, GammaAB, DeltaAB, PhA, PhB, FetchPortTypePad19};

CreateFetchIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[FetchSwitchIORec] ELSE NEW[FetchSimpleIORec];
};

CreateFetchDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[FetchDriveRec];
};

FetchExpand: PROC [thisCell: Cell, to: ExpansionReceiver] --ExpandProc-- = {
PrivateLookupNode: PROC [name: ROPE] RETURNS [node: Node] = {node _ RoseCreate.LookupNode[from: thisCell, path: LIST[name]]};
IPCmnd3A: Node _ PrivateLookupNode["IPCmnd3A"];
IPRejectB: Node _ PrivateLookupNode["IPRejectB"];
IPFaultB: Node _ PrivateLookupNode["IPFaultB"];
IPData: Node _ PrivateLookupNode["IPData"];
PCBusB: Node _ PrivateLookupNode["PCBusB"];
MacroJumpBA: Node _ PrivateLookupNode["MacroJumpBA"];
GetNextInstBA: Node _ PrivateLookupNode["GetNextInstBA"];
ResetBA: Node _ PrivateLookupNode["ResetBA"];
IPFaulted0BA: Node _ PrivateLookupNode["IPFaulted0BA"];
OpLengthBA: Node _ PrivateLookupNode["OpLengthBA"];
JumpOffsetSelAB: Node _ PrivateLookupNode["JumpOffsetSelAB"];
InstReadyAB: Node _ PrivateLookupNode["InstReadyAB"];
OpAB: Node _ PrivateLookupNode["OpAB"];
AlphaAB: Node _ PrivateLookupNode["AlphaAB"];
BetaAB: Node _ PrivateLookupNode["BetaAB"];
GammaAB: Node _ PrivateLookupNode["GammaAB"];
DeltaAB: Node _ PrivateLookupNode["DeltaAB"];
PhA: Node _ PrivateLookupNode["PhA"];
PhB: Node _ PrivateLookupNode["PhB"];
others: SymbolTable _ RoseCreate.GetOthers[otherss, "Fetch"];
FetchWtB: Node _ to.class.NodeInstance[erInstance: to.instance, name: "FetchWtB", type: EnumTypes.EnumType["IFUPLAFetchControl.WtIndexCtl"], other: RoseCreate.GetOther[others, "FetchWtB"]];
FetchingAB: Node _ to.class.NodeInstance[erInstance: to.instance, name: "FetchingAB", type: NumTypes.boolType, other: RoseCreate.GetOther[others, "FetchingAB"]];
IncrPFetchAddrBA: Node _ to.class.NodeInstance[erInstance: to.instance, name: "IncrPFetchAddrBA", type: NumTypes.boolType, other: RoseCreate.GetOther[others, "IncrPFetchAddrBA"]];
IBufWrtWdBc: Node _ to.class.NodeInstance[erInstance: to.instance, name: "IBufWrtWdBc", type: NumTypes.NumType[4], other: RoseCreate.GetOther[others, "IBufWrtWdBc"]];
IBufRdByteAc: Node _ to.class.NodeInstance[erInstance: to.instance, name: "IBufRdByteAc", type: NumTypes.NumType[16], other: RoseCreate.GetOther[others, "IBufRdByteAc"]];
BufBytesOccM1A: Node _ to.class.NodeInstance[erInstance: to.instance, name: "BufBytesOccM1A", type: NumTypes.NumType[5], other: RoseCreate.GetOther[others, "BufBytesOccM1A"]];
OpLengthAB: Node _ to.class.NodeInstance[erInstance: to.instance, name: "OpLengthAB", type: NumTypes.NumType[3], other: RoseCreate.GetOther[others, "OpLengthAB"]];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "fetchControl", typeName: "FetchControl", other: RoseCreate.GetOther[others, "fetchControl"], interfaceNodes: ""];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "fetchIndexing", typeName: "FetchIndexing", other: RoseCreate.GetOther[others, "fetchIndexing"], interfaceNodes: ""];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "fetchPreDecode", typeName: "FetchPreDecode", other: RoseCreate.GetOther[others, "fetchPreDecode"], interfaceNodes: ""];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "fetchAddr", typeName: "FetchAddr", other: RoseCreate.GetOther[others, "fetchAddr"], interfaceNodes: ""];
[] _ to.class.CellInstance[erInstance: to.instance, instanceName: "fetchBuffer", typeName: "FetchBuffer", other: RoseCreate.GetOther[others, "fetchBuffer"], interfaceNodes: ""];
};

RegisterCells[];

END.

"IFUFetchImpl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUFetch.Rose of March 18, 1986 5:57:22 pm PST
created for McCreight.pa
created at March 18, 1986 5:58:18 pm PST
Signal Type decls
incrPrefetch:			IncrPFetchAddrBA,
rd:						FetchRdB,
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