<> <> <> <> <> Directory Dragon, DragOpsCross; Imports BitOps, IFUPLAStackControl; CELLTYPE "StackControl" PORTS [ Push3BA < BOOL, -- from ControlPipe Pop3BA < BOOL, X1ASrcStackBA < BOOL, -- from InstrDecode X1ADstStackBA < BOOL, XBusStackEldestBA < BOOL, -- otherwise youngest XBusStackLBA < BOOL, -- otherwise PC TosAB < INT[5], -- unused BosAB < INT[5], -- unused DifBA < INT[5], -- Tos-Bos = -1 means empty, 0 means single entry, > nearlyFullDepth means nearlyFull <<>> IStkNearlyFullBA > BOOL, -- to MainControl <<>> AdjTosA > BOOL, -- to StackPtrs AddendIsOnesA > BOOL, CarryIsOneA > BOOL, StkLdLAc > INT[16], -- to StkBuffer StkLdPAc > INT[16], StkRdAc > INT[16], PhA < BOOL, PhB < BOOL ] State stkLdPBA: IFUPLAStackControl.SixteenBits, stkLdLBA: IFUPLAStackControl.SixteenBits, stkRdBA: IFUPLAStackControl.SixteenBits EvalSimple IF PhA THEN { [[ adjTos: AdjTosA, addendIsOnes: AddendIsOnesA, carryIsOne: CarryIsOneA ]] _ IFUPLAStackControl.StackAControlProc[[ diff: DifBA, -- unused x1ASrcStack: X1ASrcStackBA, x1ADstStack: X1ADstStackBA, xBusStackEldest: XBusStackEldestBA, xBusStackL: XBusStackLBA, push3: Push3BA, pop3: Pop3BA ]]; StkLdLAc _ stkLdLBA; StkLdPAc _ stkLdPBA; StkRdAc _ stkRdBA; } ELSE {StkLdLAc _ StkLdPAc _ StkRdAc _ 0}; IF PhB THEN { [[ iStkNearlyFull: IStkNearlyFullBA ]] _ IFUPLAStackControl.StackBControlProc[[ diff: DifBA, x1ASrcStack: X1ASrcStackBA, -- unused x1ADstStack: X1ADstStackBA, -- unused xBusStackEldest: XBusStackEldestBA, -- unused xBusStackL: XBusStackLBA, -- unused push3: Push3BA, pop3: Pop3BA -- unused ]]; [[ stkLdP: stkLdPBA, stkLdL: stkLdLBA, stkRd: stkRdBA ]] _ IFUPLAStackControl.StackDecodeProc[[ tos: TosAB, bos: BosAB, diff: DifBA, -- unused x1ASrcStack: X1ASrcStackBA, x1ADstStack: X1ADstStackBA, xBusStackEldest: XBusStackEldestBA, xBusStackL: XBusStackLBA, push3: Push3BA, pop3: Pop3BA ]]; }; ENDCELLTYPE; CELLTYPE "StackPtrs" PORTS [ AdjTosA < BOOL, -- from StackControl AddendIsOnesA < BOOL, CarryIsOneA < BOOL, TosAB > INT[5], -- Tos=Bos-1 means empty, Tos=Bos means one entry BosAB > INT[5], DifBA > INT[5], ResetBA < BOOL, PhA < BOOL, PhB < BOOL ] State tosAB, tosBA: [0..32), bosAB, bosBA: [0..32), difBA: [0..32) EvalSimple IF PhA THEN { adderMuxA: [0..32) = IF AdjTosA THEN tosBA ELSE bosBA; addendA: [0..32) = IF AddendIsOnesA THEN 31 ELSE 0; carryA: [0..1] = IF CarryIsOneA THEN 1 ELSE 0; sumA: [0..32) = (adderMuxA+addendA+carryA) MOD 32; TosAB _ tosAB _ SELECT TRUE FROM ResetBA => 0, AdjTosA => sumA, ENDCASE => tosBA; -- needed because AdjTosA might glitch BosAB _ bosAB _ SELECT TRUE FROM ResetBA => 1, NOT AdjTosA => sumA, ENDCASE => bosBA; -- needed because AdjTosA might glitch }; IF PhB THEN { DifBA _ difBA _ (32+tosAB-bosAB) MOD 32; tosBA _ tosAB; bosBA _ bosAB; }; ENDCELLTYPE; <> <> <<>> <> <> <> <<>> <> <> <<>> <> <<>> <<>> <> <> <<>> <> <> <<>> <> <<>> <> <> <> < stkLdLBA[(TosAB+1) MOD 16] _ TRUE;>> <>> <> <>> <> < NULL;>> <<};>> <<>> <> <<>> <> <<>> <<>> <> <> <<>> <> <> <> <<>> <> <> <<>> <> <<>> <<>> <> <> <<>> <> <> <<>> <> <<>> <> <> <> < stkLdPBA[(TosAB+1) MOD 16] _ TRUE;>> <>> <> <>> <> < NULL;>> <<};>> <<>> <> <<>> <> <<>> <<>> <> <> <<>> <> <> <<>> <> <> <<>> <> <<>> <<>> <> <> <<>> <> <> <<>> <> <<>> <> <> <> <> <>> <> < stkRdBA[(TosAB+31) MOD 16] _ TRUE;>> < stkRdBA[BosAB MOD 16] _ TRUE;>> < ERROR;>> <<};>> <<>> <> <<>> <> CELLTYPE "StackBuffer" PORTS [ XBus = INT[32], PCPipe3BA < INT[32], -- PCHandler PCStkTopAB > INT[32], LPipe3BA < INT[8], -- LPipe LStkTopAB > INT[8], X1ASrcStackBA < BOOL, -- from InstrDecode X1ADstStackBA < BOOL, XBusStackEldestBA < BOOL, -- otherwise youngest XBusStackLBA < BOOL, -- otherwise PC StkRdAc < INT[16], StkLdLAc < INT[16], StkLdPAc < INT[16], <<>> Push3BA < BOOL, -- for pipeline bypass PhA < BOOL, PhB < BOOL ] State pStack: ARRAY [0..16) OF Dragon.HexWord, pRdBufA, pWrtBufA: Dragon.HexWord, lStack: ARRAY [0..16) OF Dragon.HexByte, lRdBufA, lWrtBufA: Dragon.HexByte EvalSimple IF X1ADstStackBA THEN { pWrtBufA _ BitOps.ELFD[XBus, 32, 0, 32]; lWrtBufA _ BitOps.ELFD[XBus, 32, 24, 8]; } ELSE { pWrtBufA _ BitOps.ELFD[PCPipe3BA, 32, 0, 32]; lWrtBufA _ LPipe3BA; }; FOR index: NAT IN [0..16) DO EB: PROC[w: BitOps.BitWord] RETURNS[BOOL] = {TRUSTED{RETURN[LOOPHOLE[w, PACKED ARRAY [0..16) OF BOOL][index]]}}; IF EB[StkRdAc] THEN {lRdBufA _ lStack[index]; pRdBufA _ pStack[index]}; IF EB[StkLdLAc] THEN lStack[index] _ lWrtBufA; IF EB[StkLdPAc] THEN pStack[index] _ pWrtBufA; ENDLOOP; IF Push3BA THEN {pRdBufA _ pWrtBufA; lRdBufA _ lWrtBufA}; -- bypass IF PhA AND X1ASrcStackBA THEN { drive[XBus] _ drive; XBus _ BitOps.ILID[(IF XBusStackLBA THEN lRdBufA ELSE pRdBufA), XBus, 32, 0, 32]; } ELSE drive[XBus] _ ignore; IF PhA THEN {PCStkTopAB _ BitOps.ILID[pRdBufA, PCStkTopAB, 32, 0, 32]; LStkTopAB _ lRdBufA}; ENDCELLTYPE; CELLTYPE "Stack" PORTS [ <<>> XBus = INT[32], PCPipe3BA < INT[32], PCStkTopAB > INT[32], LPipe3BA < INT[8], LStkTopAB > INT[8], LBusB > INT[8], Push3BA < BOOL, -- from ControlPipe Pop3BA < BOOL, X1ASrcStackBA < BOOL, -- from InstrDecode X1ADstStackBA < BOOL, XBusStackEldestBA < BOOL, XBusStackLBA < BOOL, IStkNearlyFullBA > BOOL, -- to MainControl <<>> ResetBA < BOOL, PhA < BOOL, PhB < BOOL ] Expand DifBA: INT[5]; -- StackPtrs to StackControl <<>> AdjTosA: BOOL; -- StackControl to StackPtrs AddendIsOnesA: BOOL; CarryIsOneA: BOOL; TosAB: INT[5]; -- StackPtrs to WriteStack*Ena, ReadStackEna BosAB: INT[5]; <<>> StkLdPAc: INT[16]; -- WriteStackPEna to StackBuffer StkLdLAc: INT[16]; -- WriteStackLEna to StackBuffer StkRdAc: INT[16]; -- ReadStackEna to StackBuffer stackControl: StackControl[]; stackPtrs: StackPtrs[]; <> <> <> stackBuffer: StackBuffer[] -- data column ENDCELLTYPE