<> <> <> <> <<>> <> <> <> Directory DragOpsCross; TranslationNeeds Dragon, IFUPLAFetchControl, IFUPLAFetchPreDecode; Imports BitOps, DragonRosemary, DragonRoseExtras, IFUPLAFetchControl, IFUPLAFetchPreDecode; CELLTYPE "FetchControl" PORTS [ <<>> <> IPCmnd3A > EnumType["Dragon.PBusCommands"], IPRejectB < BOOL, IPFaultB < EnumType["Dragon.PBusFaults"], <> MacroJumpBA < BOOL, -- from InstrDecode IPFaulted0BA > BOOL, -- to ControlPipe IncrPFetchAddrBA > BOOL, -- to FetchAddr <> ResetBA < BOOL, <> BufBytesOccM1A < INT[5], -- from FetchIndexing < EnumType["IFUPLAFetchControl.RdIndexCtl"], -- to FetchIndex>> FetchWtB > EnumType["IFUPLAFetchControl.WtIndexCtl"], -- to FetchIndex FetchingAB > BOOL, PhA < BOOL, PhB < BOOL ] State jumpPendingAB, jumpPendingBA: BOOL, newFetchBA: BOOL, fetchingBA: BOOL, faultedAB: BOOL, bufBytesOccM1AB: [0..32) EvalSimple IF PhA THEN { jumpPendingAB _ jumpPendingBA; faultedAB _ IPFaulted0BA; FetchingAB _ fetchingBA; bufBytesOccM1AB _ BufBytesOccM1A; IPCmnd3A _ IF newFetchBA THEN Fetch ELSE NoOp}; IF PhB THEN { [ [ jumpPending: jumpPendingBA, newFetch: newFetchBA, fetching: fetchingBA, faulted: IPFaulted0BA, <> <> wtIndexCtl: FetchWtB ] ] _ IFUPLAFetchControl.FetchControlProc[ [ -- Static Logic jump: MacroJumpBA, getNext: FALSE, -- not used, formerly GetNextInstBA reset: ResetBA, reject: IPRejectB, jumpPending: jumpPendingAB, fetching: FetchingAB, bytesOccM1: bufBytesOccM1AB, faulted: faultedAB, ipPageFault: IPFaultB=page ] ]; IncrPFetchAddrBA _ newFetchBA }; ENDCELLTYPE; CELLTYPE "FetchIndexing" PORTS [ <> FetchWtB < EnumType["IFUPLAFetchControl.WtIndexCtl"], -- from FetchControl FetchingAB < BOOL, PCBusB < INT[32], OpLengthAB < INT[3], -- from FetchPreDecode GetNextInstBA < BOOL, -- from InstrDecode MacroJumpBA < BOOL, -- from InstrDecode <<>> IBufWrtWdBc > INT[4], -- to FetchBuffer IBufRdByteAc > INT[16], BufBytesOccM1A > INT[5], -- to FetchPreDecode, FetchControl PhA < BOOL, PhB < BOOL ] State wtAB, wtBA: [0..8), rdAB, rdBA: [0..32) EvalSimple IF PhA THEN { wtAB _ wtBA; rdAB _ rdBA; IBufRdByteAc _ BitOps.IBIW[TRUE, 0, 16, rdBA MOD 16] } ELSE IBufRdByteAc _ 0; IF PhB THEN { SELECT FetchWtB FROM clear => wtBA _ 0; hold => wtBA _ wtAB; inc => wtBA _ (wtAB+1) MOD 8; ENDCASE => DragonRosemary.Assert[FALSE, "Hello?"]; rdBA _ (SELECT TRUE FROM MacroJumpBA => (DragonRoseExtras.LFD[PCBusB] MOD DragOpsCross.bytesPerWord), GetNextInstBA => (rdAB+OpLengthAB) MOD 32, ENDCASE => rdAB); IF FetchingAB THEN IBufWrtWdBc _ BitOps.IBIW[TRUE, 0, 4, wtAB MOD 4] ELSE IBufWrtWdBc _ 0; } ELSE IBufWrtWdBc _ 0; BufBytesOccM1A _ (4*wtBA-rdBA-1+64) MOD 32; ENDCELLTYPE; CELLTYPE "FetchPreDecode" PORTS [ <<>> OpAB < INT[8], <<>> BufBytesOccM1A < INT[5], -- from FetchIndexing OpLengthAB > INT[3], JumpOffsetSelAB > EnumType["IFUPLAFetchPreDecode.JumpOffsetSel"], OpLengthBA > INT[3], InstReadyAB > BOOL, PhA < BOOL, PhB < BOOL ] EvalSimple IF PhA THEN { notInstReady: BOOL; [ [ opLength: OpLengthAB, jumpOffset: JumpOffsetSelAB, notInstReady: notInstReady ] ] _ IFUPLAFetchPreDecode.FetchPreDecodeProc[ [ -- Static logic preOp: LOOPHOLE[OpAB], bytesOccM1: BufBytesOccM1A ] ]; IF DragonRosemary.OpLength[OpAB]#OpLengthAB THEN DragonRosemary.Assert[FALSE, "DragonImpl.OpLength # IFUPLAFetchPreDecode.GenFetchPreDecodePLA"]; InstReadyAB _ NOT notInstReady }; IF PhB THEN OpLengthBA _ OpLengthAB; ENDCELLTYPE; CELLTYPE "FetchAddr" PORTS [ IPData = INT[32], PCBusB < INT[32], MacroJumpBA < BOOL, IncrPFetchAddrBA < BOOL, PhA < BOOL, PhB < BOOL ] State errorAB: BOOL, --not used !!! JH fetchAddrBA: Dragon.HexWord, fetchAddrAB: Dragon.HexWord EvalSimple drive[IPData] _ IF PhA THEN drive ELSE ignore; IF PhA THEN { IPData _ DragonRoseExtras.LTD[fetchAddrBA/4]; -- Byte to word happens here IF IncrPFetchAddrBA THEN fetchAddrAB _ fetchAddrBA+4 -- byte offset in loc 30,31 ELSE fetchAddrAB _ fetchAddrBA }; IF PhB THEN { IF MacroJumpBA THEN fetchAddrBA _ DragonRoseExtras.LFD[PCBusB] ELSE fetchAddrBA _ fetchAddrAB }; ENDCELLTYPE; CELLTYPE "FetchBuffer" PORTS [ IPData < INT[32], IBufWrtWdBc < INT[4], IBufRdByteAc < INT[16], OpAB > INT[8], AlphaAB > INT[8], BetaAB > INT[8], GammaAB > INT[8], DeltaAB > INT[8], PhA < BOOL, PhB < BOOL ] State preOpA: Dragon.HexByte, preAlphaA: Dragon.HexByte, preBetaA: Dragon.HexByte, preGammaA: Dragon.HexByte, preDeltaA: Dragon.HexByte, iBuf: ARRAY [0..16) OF Dragon.HexByte EvalSimple FOR j: [0..4) IN [0..4) DO IF BitOps.EBFW[IBufWrtWdBc, 4, j] THEN FOR k: NAT IN [0..4) DO iBuf[4*j+k] _ BitOps.ECFD[IPData, 32, 8*k, 8]; ENDLOOP; ENDLOOP; FOR j: [0..16) IN [0..16) DO IF BitOps.EBFW[IBufRdByteAc, 16, j] THEN { preOpA _ BitOps.WAND[preOpA, iBuf[j]]; preAlphaA _ BitOps.WAND[preAlphaA, iBuf[(j+1) MOD 16]]; preBetaA _ BitOps.WAND[preBetaA, iBuf[(j+2) MOD 16]]; preGammaA _ BitOps.WAND[preGammaA, iBuf[(j+3) MOD 16]]; preDeltaA _ BitOps.WAND[preDeltaA, iBuf[(j+4) MOD 16]] }; ENDLOOP; IF PhA THEN { OpAB _ preOpA; AlphaAB _ preAlphaA; BetaAB _ preBetaA; GammaAB _ preGammaA; DeltaAB _ preDeltaA }; IF PhB THEN { preOpA _ 255; preAlphaA _ 255; preBetaA _ 255; preGammaA _ 255; preDeltaA _ 255 }; ENDCELLTYPE; CELLTYPE "Fetch" PORTS [ IPCmnd3A > EnumType["Dragon.PBusCommands"], IPRejectB < BOOL, IPFaultB < EnumType["Dragon.PBusFaults"], --not used !!! JH IPData = INT[32], PCBusB < INT[32], MacroJumpBA < BOOL, -- from InstrDecode to FetchControl, Addr GetNextInstBA < BOOL, -- from InstrDecode to FetchControl ResetBA < BOOL, IPFaulted0BA > BOOL, -- FetchControl to ControlPipe OpLengthBA > INT[3], -- FetchPreDecode to PCFormation JumpOffsetSelAB > EnumType["IFUPLAFetchPreDecode.JumpOffsetSel"], InstReadyAB > BOOL, OpAB > INT[8], AlphaAB > INT[8], BetaAB > INT[8], GammaAB > INT[8], DeltaAB > INT[8], PhA < BOOL, PhB < BOOL ] Expand <> FetchWtB: EnumType["IFUPLAFetchControl.WtIndexCtl"]; -- to FetchIndex FetchingAB: BOOL; IncrPFetchAddrBA: BOOL; -- FetchControl to FetchAddr IBufWrtWdBc: INT[4], -- FetchIndex to FetchBuffer IBufRdByteAc: INT[16], BufBytesOccM1A: INT[5], -- FetchIndex to FetchPreDecode, FetchControl OpLengthAB: INT[3], -- FetchPreDecode to FetchControl fetchControl: FetchControl[]; -- control column fetchIndexing: FetchIndexing[]; -- control column fetchPreDecode: FetchPreDecode[]; -- control column fetchAddr: FetchAddr[]; -- data column fetchBuffer: FetchBuffer[] -- data column ENDCELLTYPE