IFUData1Impl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUData1.Rose of March 18, 1986 5:35:29 pm PST
created for McCreight.pa
created at March 18, 1986 5:35:44 pm PST
DIRECTORY
RoseTypes, IFUData1, RoseCreate, DragOpsCross, IFUPLAMainControl, IFUPLAInstrDecode, DragonRoseExtras, SwitchTypes, IFUPLAFetchPreDecode, Dragon;
IFUData1Impl:
CEDAR
PROGRAM
IMPORTS RoseCreate, DragonRoseExtras
EXPORTS IFUData1
=
BEGIN
OPEN
RoseTypes, IFUData1;
Signal Type decls
X2ALitSource: TYPE = IFUPLAInstrDecode.X2ALitSource;
PCBusSrc: TYPE = IFUPLAInstrDecode.PCBusSrc;
PCPipeSrc: TYPE = IFUPLAInstrDecode.PCPipeSrc;
PCNext: TYPE = IFUPLAInstrDecode.PCNext;
JumpOffsetSel: TYPE = IFUPLAFetchPreDecode.JumpOffsetSel;
ExceptionCode: TYPE = IFUPLAMainControl.ExceptionCode;
PBusFaults: TYPE = Dragon.PBusFaults;
CondSelects: TYPE = Dragon.CondSelects;
RegisterCells:
PROC =
BEGIN
X2ALitGen ← RoseCreate.RegisterCellType[name: "X2ALitGen",
expandProc: NIL,
ioCreator: CreateX2ALitGenIO, driveCreator: CreateX2ALitGenDrive, initializer: InitializeX2ALitGen,
evals: [EvalSimple: X2ALitGenEvalSimple],
tests: LIST[],
ports: CreateX2ALitGenPorts[]
];
PCForm ← RoseCreate.RegisterCellType[name: "PCForm",
expandProc: NIL,
ioCreator: CreatePCFormIO, driveCreator: CreatePCFormDrive, initializer: InitializePCForm,
evals: [EvalSimple: PCFormEvalSimple],
tests: LIST[],
ports: CreatePCFormPorts[]
];
END;
otherss: SymbolTable ← RoseCreate.GetOtherss["IFUData1.partsAssertions"];
X2ALitGen: PUBLIC CellType;
CreateX2ALitGenPorts: PROC RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["IFUData1.X2ALitGen.rosePorts"]};
X2ALitGenSwitchIORef: TYPE = REF X2ALitGenSwitchIORec;
X2ALitGenSwitchIORec:
TYPE =
RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,AlphaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BetaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,GammaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DeltaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,X2ALitSourceBA: PACKED ARRAY [0 .. 5) OF SwitchTypes.SwitchVal
,X2ASrcLit1BA: SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];
X2ALitGenSimpleIORef: TYPE = REF X2ALitGenSimpleIORec;
X2ALitGenSimpleIORec:
TYPE =
RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,fill1: [0 .. 255],
AlphaAB: [0..255]
,fill2: [0 .. 255],
BetaAB: [0..255]
,fill3: [0 .. 255],
GammaAB: [0..255]
,fill4: [0 .. 255],
DeltaAB: [0..255]
,fill5: [0 .. 2047],
X2ALitSourceBA: X2ALitSource
,fill6: [0 .. 32767],
X2ASrcLit1BA: BOOLEAN
,fill7: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill8: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill9: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill10: [0 .. 32767],
PhA: BOOLEAN
,fill11: [0 .. 32767],
PhB: BOOLEAN
];
X2ALitGenDriveRef: TYPE = REF X2ALitGenDriveRec;
X2ALitGenDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY X2ALitGenPort OF DriveLevel];
X2ALitGenPort:
TYPE = {
XBus, AlphaAB, BetaAB, GammaAB, DeltaAB, X2ALitSourceBA, X2ASrcLit1BA, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, PhA, PhB};
CreateX2ALitGenIO:
PROC [ct: CellType, switch:
BOOL]
RETURNS [ioAsAny:
REF
ANY]
--IOCreator-- = {
ioAsAny ← IF switch THEN NEW[X2ALitGenSwitchIORec] ELSE NEW[X2ALitGenSimpleIORec];
};
CreateX2ALitGenDrive:
PROC [ct: CellType]
RETURNS [driveAsAny:
REF
ANY]
--DriveCreator-- = {
driveAsAny ← NEW[X2ALitGenDriveRec];
};
X2ALitGenStateRef: TYPE = REF X2ALitGenStateRec;
X2ALitGenStateRec:
TYPE =
RECORD [
xaPipe0BA, xaPipe1AB, xaPipe1BA: Dragon.HexWord
];
InitializeX2ALitGen: Initializer = {
state: X2ALitGenStateRef ← NEW[X2ALitGenStateRec];
cell.realCellStuff.state ← state;
};
X2ALitGenEvalSimple: SimpleEval =
BEGIN
drive: X2ALitGenDriveRef ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: X2ALitGenSwitchIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: X2ALitGenSimpleIORef ← NARROW[cell.realCellStuff.newIO];
state: X2ALitGenStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN
OPEN drive, newIO, state;
IF PhB
THEN
xaPipe0BA ←
SELECT X2ALitSourceBA
FROM
alpha => AlphaAB,
beta => BetaAB,
alphaBeta => AlphaAB*LONG[256] + BetaAB,
alpBetGamDel => ((AlphaAB*LONG[256] + BetaAB)*256 + GammaAB)*256 + DeltaAB,
ENDCASE => AlphaAB -- don't care -- ;
IF LoadStage1Ac THEN xaPipe1AB ← xaPipe0BA;
IF LoadStage1Bc THEN xaPipe1BA ← xaPipe1AB;
IF PhA
AND X2ASrcLit1BA
THEN {
drive[XBus] ← drive;
XBus ← DragonRoseExtras.LTD[xaPipe1BA]
} ELSE drive[XBus] ← ignore;
END;
END;
PCForm: PUBLIC CellType;
CreatePCFormPorts: PROC RETURNS [ports: Ports] = {ports ← RoseCreate.PortsFromFile["IFUData1.PCForm.rosePorts"]};
PCFormSwitchIORef: TYPE = REF PCFormSwitchIORec;
PCFormSwitchIORec:
TYPE =
RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCPipe3BA: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCStkTopAB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCBusB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PCBusSrcB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,PCPipeSrcBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,PCNextBA: PACKED ARRAY [0 .. 1) OF SwitchTypes.SwitchVal
,OpLengthBA: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,JumpOffsetSelAB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,OpAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,AlphaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BetaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,GammaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DeltaAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,OpBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,AlphaBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,BetaBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,AbortStage3A2BA: SwitchTypes.SwitchVal
,NormalStage3A2BA: SwitchTypes.SwitchVal
,ExceptionCodeAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DPFaultB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,EUCondSel3AB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,PCForLogAB: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];
PCFormSimpleIORef: TYPE = REF PCFormSimpleIORec;
PCFormSimpleIORec:
TYPE =
RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,PCPipe3BA: ARRAY [0..2) OF CARDINAL
,PCStkTopAB: ARRAY [0..2) OF CARDINAL
,PCBusB: ARRAY [0..2) OF CARDINAL
,fill4: [0 .. 255],
PCBusSrcB: PCBusSrc
,fill5: [0 .. 8191],
PCPipeSrcBA: PCPipeSrc
,fill6: [0 .. 32767],
PCNextBA: PCNext
,fill7: [0 .. 8191],
OpLengthBA: [0..7]
,fill8: [0 .. 4095],
JumpOffsetSelAB: JumpOffsetSel
,fill9: [0 .. 255],
OpAB: [0..255]
,fill10: [0 .. 255],
AlphaAB: [0..255]
,fill11: [0 .. 255],
BetaAB: [0..255]
,fill12: [0 .. 255],
GammaAB: [0..255]
,fill13: [0 .. 255],
DeltaAB: [0..255]
,fill14: [0 .. 255],
OpBA: [0..255]
,fill15: [0 .. 255],
AlphaBA: [0..255]
,fill16: [0 .. 255],
BetaBA: [0..255]
,fill17: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill18: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill19: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill20: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill21: [0 .. 32767],
AbortStage3A2BA: BOOLEAN
,fill22: [0 .. 32767],
NormalStage3A2BA: BOOLEAN
,fill23: [0 .. 255],
ExceptionCodeAB: ExceptionCode
,fill24: [0 .. 4095],
DPFaultB: PBusFaults
,fill25: [0 .. 4095],
EUCondSel3AB: CondSelects
,PCForLogAB: ARRAY [0..2) OF CARDINAL
,fill27: [0 .. 32767],
PhA: BOOLEAN
,fill28: [0 .. 32767],
PhB: BOOLEAN
];
PCFormDriveRef: TYPE = REF PCFormDriveRec;
PCFormDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY PCFormPort OF DriveLevel];
PCFormPort:
TYPE = {
XBus, PCPipe3BA, PCStkTopAB, PCBusB, PCBusSrcB, PCPipeSrcBA, PCNextBA, OpLengthBA, JumpOffsetSelAB, OpAB, AlphaAB, BetaAB, GammaAB, DeltaAB, OpBA, AlphaBA, BetaBA, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, LoadStage3Ac, AbortStage3A2BA, NormalStage3A2BA, ExceptionCodeAB, DPFaultB, EUCondSel3AB, PCForLogAB, PhA, PhB, PCFormPortTypePad29, PCFormPortTypePad30, PCFormPortTypePad31};
CreatePCFormIO:
PROC [ct: CellType, switch:
BOOL]
RETURNS [ioAsAny:
REF
ANY]
--IOCreator-- = {
ioAsAny ← IF switch THEN NEW[PCFormSwitchIORec] ELSE NEW[PCFormSimpleIORec];
};
CreatePCFormDrive:
PROC [ct: CellType]
RETURNS [driveAsAny:
REF
ANY]
--DriveCreator-- = {
driveAsAny ← NEW[PCFormDriveRec];
};
PCFormStateRef: TYPE = REF PCFormStateRec;
PCFormStateRec:
TYPE =
RECORD [
npcBA: Dragon.HexWord, -- latch on PCBusB
pcSum: Dragon.HexWord, -- adder output
pcBranchOSetB: Dragon.HexWord, -- mux for one arm of adder during PhB
xAB: Dragon.HexWord, -- latch on XBus
pcPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexWord,
pcAltPipe: ARRAY [0..2] OF ARRAY Dragon.Phase OF Dragon.HexWord,
pcAB, pcBA: Dragon.HexWord, -- the PC for this instruction
targetPCBA: Dragon.HexWord,
dpFaultAB, dpFaultBA: Dragon.PBusFaults
];
InitializePCForm: Initializer = {
state: PCFormStateRef ← NEW[PCFormStateRec];
cell.realCellStuff.state ← state;
};
PCFormEvalSimple: SimpleEval =
BEGIN
drive: PCFormDriveRef ← NARROW[cell.realCellStuff.newDriveAsAny];
sw: PCFormSwitchIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: PCFormSimpleIORef ← NARROW[cell.realCellStuff.newIO];
state: PCFormStateRef ←
NARROW[cell.realCellStuff.state];
BEGIN
OPEN drive, newIO, state;
There are three PC values that may be needed for an instruction: the PC of the instruction itself, the PC of the next sequential instruction, and the PC of a call or jump target. The instruction PC is carried down pcPipe. One of the other two PC's, which may be needed as the return address of a call-type instruction or as the alternate PC of a failed conditional jump, is carried down altPcPipe. The third PC, if any, is passed immediately to the prefetcher.
The two pipelined PC's merge at stage 3A, based on conditions computed at stage 2B. In the normal case, the merged value is altPc. In case of a trap or fault, the merged value is the pc of the offending instruction, carried in pcPipe.
SExtnd:
PROC[b: Dragon.HexByte]
RETURNS [
INT] = {
RETURN[ IF b>=128 THEN (LONG[b]-256) ELSE LONG[b]] };
IF LoadStage1Ac
THEN {
pcPipe[1][a] ← pcBA;
pcAltPipe[1][a] ←
SELECT PCPipeSrcBA
FROM
seqPC => pcSum -- next sequential instruction -- ,
offSetPC => targetPCBA -- jump target instruction -- ,
thisPC => pcBA -- for traps that are recognized only at stage 0 -- ,
ENDCASE => ERROR;
};
Memory reference instructions fail within stage 3, so they must specify PCLSPipeSrcBA = old. This shouldn't be a problem, since the only instructions that need to do otherwise are conditional jumps.
IF LoadStage1Bc THEN {pcPipe[1][b] ← pcPipe[1][a]; pcAltPipe[1][b] ← pcAltPipe[1][a]};
IF LoadStage2Ac THEN {pcPipe[2][a] ← pcPipe[1][b]; pcAltPipe[2][a] ← pcAltPipe[1][b]};
IF PhB THEN {pcPipe[2][b] ← pcPipe[2][a]; pcAltPipe[2][b] ← pcAltPipe[2][a]};
IF LoadStage3Ac
THEN {
pcPipe[3][a] ← (
SELECT
TRUE
FROM
AbortStage3A2BA => pcPipe[2][b], -- pc of aborting micro
NormalStage3A2BA => pcAltPipe[2][b], -- whatever top of pipe suggested
ENDCASE => ERROR)
};
IF PhB THEN {pcPipe[3][b] ← pcPipe[3][a]};
PCPipe3BA ← DragonRoseExtras.LTD[pcPipe[3][b]];
IF PhA THEN {
pcSum ← OpLengthBA + pcBA;
pcAB ←
SELECT PCNextBA
FROM
incr => pcSum,
fromPCBus => npcBA,
ENDCASE => ERROR;
PCForLogAB ← DragonRoseExtras.LTD[pcAB];
xAB ← DragonRoseExtras.LFD[XBus];
dpFaultAB ← dpFaultBA;
};
IF PhB THEN {
pcBranchOSetB ← (
SELECT JumpOffsetSelAB
FROM
alpha => SExtnd[AlphaAB],
beta => SExtnd[BetaAB],
alphaBeta => SExtnd[AlphaAB]*256 + BetaAB,
xAB => xAB,
ENDCASE => 0 -- shouldn't care, this will generate a jump-to-self so we'll notice -- );
targetPCBA ← pcSum ← pcBranchOSetB + pcAB;
pcBA ← pcAB;
PCBusB ← DragonRoseExtras.
LTD[(npcBA ← (
SELECT PCBusSrcB
FROM
offSetPC => pcSum,
pc => pcAB,
xA => xAB,
xopGen => DragOpsCross.bytesPerWord*(DragOpsCross.XopBase + DragOpsCross.TrapWidthWords*OpAB),
trapGen => DragOpsCross.bytesPerWord* (DragOpsCross.TrapBase+DragOpsCross.TrapWidthWords*(
SELECT ExceptionCodeAB
FROM
cTrap => 20B
-- = DragOpsCross.TrapIndex[ALUCondFalse].ORD --
+EUCondSel3AB.ORD,
dpFault => 40B
-- = DragOpsCross.TrapIndex[EUPageFault].ORD-1 --
+(dpFaultAB.ORD MOD 8),
ENDCASE => ExceptionCodeAB.ORD MOD 20B)),
alpBetGamDel => ((AlphaAB*LONG[256]+BetaAB)*256+GammaAB)*256+DeltaAB,
pipe3 => DragonRoseExtras.LFD[PCPipe3BA],
stack => DragonRoseExtras.LFD[PCStkTopAB],
ENDCASE => ERROR))];
OpBA ← OpAB;
AlphaBA ← AlphaAB;
BetaBA ← BetaAB;
dpFaultBA ← DPFaultB;
};
END;
END;
RegisterCells[];
END.