[Indigo]<Dragon>IFU>Rosemary>IFU.rose!72

IFU.rose

Last Edited by: Barth, February 8, 1984 10:51 am

Last Edited by: Twilliams, August 28, 1984 9:15:49 am PDT

Last edited by: Herrmann, September 12, 1985 6:23:08 pm PDT

Last edited by: McCreight, March 18, 1986 3:23:57 pm PST

Last edited by: Curry, September 24, 1985 7:59:28 pm PDT

Signal names obey the following conventions: If a signal x is computed during PhA and remains valid throughout the following PhB, it is denoted as xAB and is said to be stable. If x is computed (combinatorialy) during PhA and can have unrestrained changes during PhB and the first part of phase A, it is denoted as xA and is said to be floppy. In this latter case, a client wanting to use x during PhB must receive it in his own latch open during PhA. xBA and xB are defined symmetrically. A signal which is low while A is low and can have at most one transition while A is high is denoted as xAc and is said to a control clock. A signal which is high while A is low and can have at most one transition during A is denoted as NxAc. Although precharged signals have the single transistion property they must be gated with the appropiate clock in order to achive the status of being a control clock.

Floppy signals may not be used as inputs to precharged PLA's.

Examples:

xA floppy

xAB stable

xAc BA or precharged low signal gated with phase A.

Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., PNPError for PBus Negative-TRUE Parity Error).ALSE

Directory DragOpsCross, IFUPLAMainControl, IFUPLAInstrDecode, LizardRosemary;

TranslationNeeds Dragon, IFUPLAMainControl, IFUPLAInstrDecode, IFUPLAFetchPreDecode;

Library IFUData1, IFUData2LS, IFUData2ABC, IFUData3, IFUFetch, IFUStack, IFUMainControl, IFUInterlock, IFUInstrDecode;

IFU: LAMBDA [logRef: |REF IO.STREAM|, lizardSimRef: |REF LizardRosemary.Simulation| ] RETURN CELLTYPE AutoName

PORTS [

EU

KBus = INT[32],

PhA IFU <-> EU

PhB , PhB A,B,C,EUAluLeftSrc1B,EUAluRightSrc1B,EUStore2ASrc1B to EU

EUAluOp2AB > EnumType["Dragon.ALUOps"],

EUCondSel2AB > EnumType["Dragon.CondSelects"],

EUSt3AisCBus2BA > BOOL,

EUCondition2B < BOOL,

EURes3BisPBus3AB > BOOL,

EUWriteToPBus3AB > BOOL,

P Interfaces for EU cache

DPCmnd3A > EnumType["Dragon.PBusCommands"],

DPData < INT[32], -- for logging only

DPRejectB < BOOL,

DPFaultB < EnumType["Dragon.PBusFaults"],

P Interfaces for IFU cache

IPCmnd3A > EnumType["Dragon.PBusCommands"],

IPRejectB < BOOL,

IPFaultB < EnumType["Dragon.PBusFaults"],

IPData = INT[32],

Serial debugging interface

ResetAB < BOOL,

DHoldAB < BOOL,

DShiftAB < BOOL,

DExecuteAB < BOOL,

DNSelectAB < BOOL,

DDataInAB < BOOL,

DDataOutAB = BOOL,

Timing and housekeeping interface

RescheduleAB < BOOL,

PhA < BOOL,

PhB < BOOL

]

Expand

XBus: INT[32];

X2ASrcLit0BA: BOOL; -- InstrDecode to ControlPipe

X2ASrcLit1BA: BOOL; -- ControlPipe to X2ALitGen

Stage1BHoldBA: BOOL; -- Interlock to MainControl

Stage1BHoldIfRejectBA: BOOL; -- Interlock to MainControl

LoadStage1Ac: BOOL; -- Pipe Controls

LoadStage1Bc: BOOL;

LoadStage2Ac: BOOL;

BubbleStage2A1BA: BOOL;

NormalStage2A1BA: BOOL;

AbortStage2B2AB: BOOL;

NormalStage2B2AB: BOOL;

LoadStage3Ac: BOOL;

AbortStage3A2BA: BOOL;

NormalStage3A2BA: BOOL;

MicroExcptJmpAB: EnumType["IFUPLAMainControl.MicroExcptJmp"]; -- MainControl to MicroCycle

ExceptionCodeAB: EnumType["IFUPLAMainControl.ExceptionCode"]; -- MainControl to MicroCycle, PCTrapGen, CFormation

MicroCycleAB: INT[8];

GetNextInstBA: BOOL;

MacroJumpBA: BOOL;

MicroCycleNextBA: EnumType["IFUPLAInstrDecode.MicroCycleNext"];

InstReadyAB: BOOL;

OpAB: INT[8];

AlphaAB: INT[8];

BetaAB: INT[8];

GammaAB: INT[8];

DeltaAB: INT[8];

OpBA: INT[8];

AlphaBA: INT[8];

BetaBA: INT[8];

OpLengthBA: INT[3]; -- ← "1" used to prevent BoundsFault at startup

JumpOffsetSelAB: EnumType["IFUPLAFetchPreDecode.JumpOffsetSel"];

RschWaiting2BA: BOOL;

UserMode0AB: BOOL;

TrapsEnbled2BA: BOOL;

ClearTrapsEnbledBA: BOOL;

ClearUserModeBA: BOOL;

KPadsIn0BA: BOOL; -- C address in the IFU

KPadsIn3BA: BOOL;

X2ALitSourceBA: EnumType["IFUPLAInstrDecode.X2ALitSource"];

PCBusB: INT[32];

PCStkTopAB: INT[32];

PCForLogAB: INT[32];

PCPipe3BA: INT[32];

PCNextBA: EnumType["IFUPLAInstrDecode.PCNext"];

PCBusSrcB: EnumType["IFUPLAInstrDecode.PCBusSrc"];

PCPipeSrcBA: EnumType["IFUPLAInstrDecode.PCPipeSrc"];

Push0BA: BOOL; -- InstrDecode to ControlPipe

Pop0BA: BOOL; -- InstrDecode to ControlPipe

Push2BA: BOOL; -- ControlPipe to MainControl

Push3BA: BOOL; -- ControlPipe to stack

Pop3BA: BOOL; -- ControlPipe to stack

PushPendingAB: BOOL; -- ControlPipe to InstrDecode

PopPendingAB: BOOL; -- ControlPipe to InstrDecode

PushPendingBA: BOOL; -- ControlPipe to MainControl

PopPendingBA: BOOL; -- ControlPipe to MainControl

IStkNearlyFullBA: BOOL; -- stack to MainControl

LBusB: INT[8];

LStkTopAB: INT[8];

LPipe3BA: INT[8];

LAB: INT[8];

SAB: INT[8];

DeltaSBA: INT[8];

PopSa0BA: BOOL;

PopSb0BA: BOOL;

PushSc0BA: BOOL;

LSourceLtBA: EnumType["IFUPLAInstrDecode.LSourceLt"];

LSourceRtBA: EnumType["IFUPLAInstrDecode.LSourceRt"];

SSourceLtBA: EnumType["IFUPLAInstrDecode.SSourceLt"];

SSourceRtBA: EnumType["IFUPLAInstrDecode.SSourceRt"];

ASourceLtBA: EnumType["IFUPLAInstrDecode.ABCSourceLt"];

ASourceRtBA: EnumType["IFUPLAInstrDecode.ABCSourceRt"];

ASourceOffBA: EnumType["IFUPLAInstrDecode.PlusOffset"];

BSourceLtBA: EnumType["IFUPLAInstrDecode.ABCSourceLt"];

BSourceRtBA: EnumType["IFUPLAInstrDecode.ABCSourceRt"];

BSourceOffBA: EnumType["IFUPLAInstrDecode.PlusOffset"];

CSourceLtBA: EnumType["IFUPLAInstrDecode.ABCSourceLt"];

CSourceRtBA: EnumType["IFUPLAInstrDecode.ABCSourceRt"];

CSourceOffBA: EnumType["IFUPLAInstrDecode.MinusOffset"];

X1ASrcStackBA: BOOL; -- various registers in the IFU

X1ADstStackBA: BOOL;

XBusStackEldestBA: BOOL;

XBusStackLBA: BOOL;

X1ASrcSLimitAc: BOOL;

X1ADstSLimitAc: BOOL;

X2ASrcStatusBA: BOOL;

X1ADstStatusBA: BOOL;

AReg0BA: INT[8]; -- passed up to this level just for the logger

BReg0BA: INT[8]; -- passed up to this level just for the logger

CReg0BA: INT[8]; -- passed up to this level just for the logger

ARegIsC2BA: BOOL;

ARegIsC3BA: BOOL;

BRegIsC2BA: BOOL;

BRegIsC3BA: BOOL;

ALUOpNeedsField0BA: BOOL; -- from InstrDecode to ControlPipe

ALUOpNeedsField1BA: BOOL; -- from ControlPipe to Interlock

C0IsFieldCtlBA: BOOL; -- from InstrDecode to ControlPipe

C2IsFieldCtlAB: BOOL; -- from ControlPipe to Interlock

C3IsFieldCtlAB: BOOL; -- from ControlPipe to Interlock

CRegIsField3B: BOOL; -- from ControlPipe to ABCFormation, piece of KBus

EUAluLeftSrc1B: EnumType["Dragon.ALULeftSources"],

IFUInterlock to ABCFormation, piece of KBus

EUAluRightSrc1B: EnumType["Dragon.ALURightSources"],

EUStore2ASrc1B: EnumType["Dragon.Store2ASources"],

EStkOverflow1BA: BOOL; -- SLimit to Control pipe

EStkOverflow2BA: BOOL; -- Control pipe to MainControl PLA

DPCmnd0BA: EnumType["Dragon.PBusCommands"];

DPCmndRd0BA: BOOL;

DPCmndRd2BA: BOOL;

DPCmndRd3BA: BOOL;

KIsRtOp0BA: BOOL;

KIsRtOp1BA: BOOL;

FCtlIsRtOp0BA: BOOL;

FCtlIsRtOp1BA: BOOL;

EUAluOp0BA: EnumType["Dragon.ALUOps"];

EUCondSel0BA: EnumType["Dragon.CondSelects"];

EUCondSel3AB: EnumType["Dragon.CondSelects"];

EUCondEffect0BA: EnumType["IFUPLAMainControl.CondEffect"];

EUCondEffect1BA: EnumType["IFUPLAMainControl.CondEffect"];

EUCondEffect2AB: EnumType["IFUPLAMainControl.CondEffect"];

EUCondEffect2BA: EnumType["IFUPLAMainControl.CondEffect"];

EUSt3AisCBus1BA: BOOL;

EUAluLeftSrc1AB: EnumType["Dragon.ALULeftSources"];

EUAluRightSrc1AB: EnumType["Dragon.ALURightSources"];

EUStore2ASrc1AB: EnumType["Dragon.Store2ASources"];

DPRejectedBA: BOOL;

IPFaulted0BA: BOOL;

IPFaulted2BA: BOOL;

InstStarting0BA: BOOL;

InstStarting2BA: BOOL;

RescheduleBA: BOOL;

ResetBA: BOOL;

DHold0BA: BOOL;

DHold1AB: BOOL;

logger: IFULogger[logRef: logRef, lizardSimRef: lizardSimRef][];

fetch: Fetch[]; -- IFUFetch

x2ALitGen: X2ALitGen[]; -- IFUData1

pcForm: PCForm[]; -- IFUData1

stack: Stack[]; -- IFUStack

lFormation: LFormation[]; -- IFUData2

sFormation: SFormation[]; -- IFUData2

sLimitTest: SLimitTest[]; -- IFUData2

sDelta: SDelta[]; -- IFUData2 (static control)

aBCFormation: ABCFormation[]; -- IFUData2

ifuStatus: IFUStatus[]; -- IFUData3

kBusPads: KBusPads[]; -- IFUData3

mainControl: MainControl[]; -- MainControl

microCycle: MicroCycle[]; -- MainControl

instrDecode: InstrDecode[]; -- InstrDecode

interlock: Interlock[]; -- Interlock

controlPipe: ControlPipe[]; -- Interlock

misc: Misc[] -- IFUData3

ENDCELLTYPE