DIRECTORY Commander, IFUPLAStackControl, IO, PLAOps; IFUPLAStackControlImpl: CEDAR PROGRAM IMPORTS Commander, IO, PLAOps = BEGIN OPEN PO: PLAOps; StackDecodeIn: TYPE = IFUPLAStackControl.StackDecodeIn; StackAControlIn: TYPE = IFUPLAStackControl.StackAControlIn; StackBControlIn: TYPE = IFUPLAStackControl.StackBControlIn; StackAControlOut: TYPE = IFUPLAStackControl.StackAControlOut; StackBControlOut: TYPE = IFUPLAStackControl.StackBControlOut; StackDecodeOut: TYPE = IFUPLAStackControl.StackDecodeOut; StackDecodeWtPOut: TYPE = IFUPLAStackControl.StackDecodeWtPOut; StackDecodeWtLOut: TYPE = IFUPLAStackControl.StackDecodeWtLOut; StackDecodeRdOut: TYPE = IFUPLAStackControl.StackDecodeRdOut; Index: TYPE = IFUPLAStackControl.Index; SixteenBits: TYPE = IFUPLAStackControl.SixteenBits; TosMod: Index = IFUPLAStackControl.TosMod; BosMod: Index = IFUPLAStackControl.BosMod; DiffSig: Index = IFUPLAStackControl.DiffSig; TosSig: Index = IFUPLAStackControl.TosSig; BosSig: Index = IFUPLAStackControl.BosSig; StackAControlPLA: PUBLIC PLAOps.PLA; StackBControlPLA: PUBLIC PLAOps.PLA; StackDecodePLA: PUBLIC PLAOps.PLA; StackDecodeWtPPLA: PUBLIC PLAOps.PLA; StackDecodeWtLPLA: PUBLIC PLAOps.PLA; StackDecodeRdPLA: PUBLIC PLAOps.PLA; nearlyFullDiff: Index = 10; GenStackAControlPLA: PROC = { x1ASrcStack: BE _ BEA[m:[x1ASrcStack: TRUE], d:[x1ASrcStack: TRUE]]; x1ADstStack: BE _ BEA[m:[x1ADstStack: TRUE], d:[x1ADstStack: TRUE]]; xBusStackEldest: BE _ BEA[m:[xBusStackEldest: TRUE], d:[xBusStackEldest: TRUE]]; xBusStackL: BE _ BEA[m:[xBusStackL: TRUE], d:[xBusStackL: TRUE]]; push3: BE _ BEA[m:[push3: TRUE], d:[push3: TRUE]]; pop3: BE _ BEA[m:[pop3: TRUE], d:[pop3: TRUE]]; SetA[out:[stackAdjTos: TRUE], s: PO.Or[push3, pop3] ]; SetA[out:[stackAddendIsOnes: TRUE], s: PO.Or[pop3, PO.And[x1ADstStack, xBusStackEldest, PO.Not[ xBusStackL]]] ]; SetA[out:[stackCarryIsOne: TRUE], s: PO.Or[push3, PO.And[x1ASrcStack, xBusStackEldest, PO.Not[ xBusStackL]]] ]}; GenStackBControlPLA: PROC = { trap: BE _ BEB[m:[microExcptJmpTrap: TRUE], d:[microExcptJmpTrap: TRUE]]; push3: BE _ BEB[m:[push3: TRUE], d:[push3: TRUE]]; pop3: BE _ BEB[m:[pop3: TRUE], d:[pop3: TRUE]]; pushing: BE _ PO.Or[push3, trap]; SetB[ out:[push3: TRUE], s:pushing ]; SetB[ out:[pop3: TRUE], m:[pop3: TRUE], d:[pop3: TRUE] ]; SetB[out:[iStkNearlyFull: TRUE], s: PO.And[pushing, BEB[m:[stackDiff: DiffSig], d:[stackDiff: nearlyFullDiff-1]]] ]; SetB[out:[iStkNearlyFull: TRUE], s: PO.And[PO.Not[pop3], BEB[m:[stackDiff: DiffSig], d:[stackDiff: nearlyFullDiff]]] ]; FOR diff: Index IN (nearlyFullDiff..TosMod) DO SetB[out:[iStkNearlyFull: TRUE], m:[stackDiff: DiffSig], d:[stackDiff: diff] ]; ENDLOOP }; GenStackDecodePLA: PROC = { current: BE; temp: BE; x1ASrcStack: BE _ BEDEC[m:[x1ASrcStack: TRUE], d:[x1ASrcStack: TRUE]]; x1ADstStack: BE _ BEDEC[m:[x1ADstStack: TRUE], d:[x1ADstStack: TRUE]]; xBusStackEldest: BE _ BEDEC[m:[xBusStackEldest: TRUE], d:[xBusStackEldest: TRUE]]; xBusStackL: BE _ BEDEC[m:[xBusStackL: TRUE], d:[xBusStackL: TRUE]]; push3: BE _ BEDEC[m:[push3: TRUE], d:[push3: TRUE]]; pop3: BE _ BEDEC[m:[pop3: TRUE], d:[pop3: TRUE]]; out: SixteenBits _ 1; out _ 1; temp _ PO.And[PO.Not[x1ADstStack], push3]; FOR val: Index DECREASING IN [0..TosMod) DO tos: Index _ (val-1+TosMod) MOD TosMod; -- writes above top of stack SetDec[out:[stkLdP: out], s: temp, m:[tos: TosSig], d:[tos: tos] ]; out _ out*2 ENDLOOP; current _ PO.Not[temp]; temp _ PO.And[x1ADstStack, PO.Not[xBusStackL], xBusStackEldest]; out _ 1; FOR val: Index DECREASING IN [0..BosMod) DO bos: Index _ (val+1) MOD BosMod; -- writes below bottom of stack SetDec[out:[stkLdP: out], s: PO.And[current, temp], m:[bos: BosSig], d:[bos: bos] ]; out _ out*2 ENDLOOP; current _ PO.And[current, PO.Not[temp]]; temp _ PO.And[x1ADstStack, PO.Not[xBusStackL], PO.Not[xBusStackEldest]]; out _ 1; FOR val: Index DECREASING IN [0..TosMod) DO SetDec[out:[stkLdP: out], s: PO.And[current, temp], m:[tos: TosSig], d:[tos: val] ]; out _ out*2 ENDLOOP; out _ 1; temp _ PO.And[PO.Not[x1ADstStack], push3]; FOR val: Index DECREASING IN [0..TosMod) DO tos: Index _ (val-1+TosMod) MOD TosMod; -- write above top of stack SetDec[out:[stkLdL: out], s: temp, m:[tos: TosSig], d:[tos: tos] ]; out _ out*2 ENDLOOP; current _ PO.Not[temp]; temp _ PO.And[x1ADstStack, xBusStackL, xBusStackEldest]; out _ 1; FOR val: Index DECREASING IN [0..BosMod) DO SetDec[out:[stkLdL: out], s: PO.And[current, temp], m:[bos: BosSig], d:[bos: val] ]; out _ out*2 ENDLOOP; current _ PO.And[current, PO.Not[temp]]; temp _ PO.And[x1ADstStack, xBusStackL, PO.Not[xBusStackEldest]]; out _ 1; FOR val: Index DECREASING IN [0..TosMod) DO SetDec[out:[stkLdL: out], s: PO.And[current, temp], m:[tos: TosSig], d:[tos: val] ]; out _ out*2 ENDLOOP; out _ 1; temp _ PO.And[PO.Not[xBusStackEldest], PO.Not[pop3]]; FOR val: Index DECREASING IN [0..TosMod) DO SetDec[out:[stkRd: out], s: temp, m:[tos: TosSig], d:[tos: val] ]; out _ out*2 ENDLOOP; current _ PO.Not[temp]; temp _ PO.And[PO.Not[x1ASrcStack], pop3]; out _ 1; FOR val: Index DECREASING IN [0..TosMod) DO tos: Index _ (val+1) MOD TosMod; SetDec[out:[stkRd: out], s: PO.And[current, temp], m:[tos: TosSig], d:[tos: tos] ]; out _ out*2 ENDLOOP; current _ PO.And[current, PO.Not[temp]]; temp _ PO.And[x1ASrcStack, xBusStackEldest]; out _ 1; FOR val: Index DECREASING IN [0..BosMod) DO SetDec[out:[stkRd: out], s: PO.And[current, temp], m:[bos: BosSig], d:[bos: val] ]; out _ out*2 ENDLOOP }; BE: TYPE = PO.BoolExpr; BEA: PROC [m, d: StackAControlIn] RETURNS[BE] = { mRef: REF StackAControlIn _ NARROW[StackAControlPLA.mask]; dRef: REF StackAControlIn _ NARROW[StackAControlPLA.data]; mRef^ _ m; dRef^ _ d; RETURN[PO.GetBEForDataMask[StackAControlPLA]]}; BEB: PROC [m, d: StackBControlIn] RETURNS[BE] = { mRef: REF StackBControlIn _ NARROW[StackBControlPLA.mask]; dRef: REF StackBControlIn _ NARROW[StackBControlPLA.data]; mRef^ _ m; dRef^ _ d; RETURN[PO.GetBEForDataMask[StackBControlPLA]]}; BEDEC: PROC [m, d: StackDecodeIn] RETURNS[BE] = { mRef: REF StackDecodeIn _ NARROW[StackDecodePLA.mask]; dRef: REF StackDecodeIn _ NARROW[StackDecodePLA.data]; mRef^ _ m; dRef^ _ d; RETURN[PO.GetBEForDataMask[StackDecodePLA]]}; -- only ins import SetA: PROC [s: BE _ NIL, m, d: StackAControlIn _ [ ], out: StackAControlOut] = { res: REF StackAControlOut _ NARROW[StackAControlPLA.out]; IF s=NIL THEN s _ BEA[m,d] ELSE s _ PO.And[s, BEA[m,d] ]; res^ _ out; PO.SetOutForBE[StackAControlPLA, s]}; SetB: PROC [s: BE _ NIL, m, d: StackBControlIn _ [ ], out: StackBControlOut] = { res: REF StackBControlOut _ NARROW[StackBControlPLA.out]; IF s=NIL THEN s _ BEB[m,d] ELSE s _ PO.And[s, BEB[m,d] ]; res^ _ out; PO.SetOutForBE[StackBControlPLA, s]}; SetDec: PROC [s: BE _ NIL, m, d: StackDecodeIn _ [ ], out: StackDecodeOut] = { res: REF StackDecodeOut _ NARROW[StackDecodePLA.out]; resWtP: REF StackDecodeWtPOut _ NARROW[StackDecodeWtPPLA.out]; resWtL: REF StackDecodeWtLOut _ NARROW[StackDecodeWtLPLA.out]; resRd: REF StackDecodeRdOut _ NARROW[StackDecodeRdPLA.out]; s _ IF s=NIL THEN BEDEC[m,d] ELSE PO.And[ s, BEDEC[m,d] ]; res^ _ out; PO.SetOutForBE[StackDecodePLA, s]; IF out.stkLdP#0 THEN {resWtP.stkLdP _ out.stkLdP; PO.SetOutForBE[StackDecodeWtPPLA, s]}; IF out.stkLdL#0 THEN {resWtL.stkLdL _ out.stkLdL; PO.SetOutForBE[StackDecodeWtLPLA, s]}; IF out.stkRd#0 THEN {resRd.stkRd _ out.stkRd; PO.SetOutForBE[StackDecodeRdPLA, s]}}; GenStackControl: Commander.CommandProc = { inTypeA: IO.ROPE _ "IFUPLAStackControl.StackAControlIn"; inTypeB: IO.ROPE _ "IFUPLAStackControl.StackBControlIn"; inTypeDec: IO.ROPE _ "IFUPLAStackControl.StackDecodeIn"; StackAControlPLA _ PO.NewPLA[inTypeA, "IFUPLAStackControl.StackAControlOut"]; StackBControlPLA _ PO.NewPLA[inTypeB, "IFUPLAStackControl.StackBControlOut"]; StackDecodePLA _ PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeOut"]; StackDecodeWtPPLA _ PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeWtPOut"]; StackDecodeWtLPLA _ PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeWtLOut"]; StackDecodeRdPLA _ PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeRdOut"]; GenStackAControlPLA []; GenStackBControlPLA []; GenStackDecodePLA []; [ ] _ PO.ConvertTermListToCompleteSum[StackAControlPLA.termList, FALSE,FALSE,cmd.out]; [ ] _ PO.ConvertTermListToCompleteSum[StackBControlPLA.termList, FALSE,FALSE,cmd.out]; [ ] _ PO.ConvertTermListToCompleteSum[StackDecodePLA.termList, FALSE,FALSE,cmd.out]; [ ] _ PO.ConvertTermListToCompleteSum[StackDecodeWtPPLA.termList, FALSE,FALSE,cmd.out]; [ ] _ PO.ConvertTermListToCompleteSum[StackDecodeWtLPLA.termList, FALSE,FALSE,cmd.out]; [ ] _ PO.ConvertTermListToCompleteSum[StackDecodeRdPLA.termList, FALSE,FALSE,cmd.out]; [ ] _ PO.FindAMinimalCover[StackAControlPLA.termList, 120, cmd.out]; [ ] _ PO.FindAMinimalCover[StackBControlPLA.termList, 120, cmd.out]; [ ] _ PO.FindAMinimalCover[StackDecodePLA.termList, 120, cmd.out]; [ ] _ PO.FindAMinimalCover[StackDecodeWtPPLA.termList, 120, cmd.out]; [ ] _ PO.FindAMinimalCover[StackDecodeWtLPLA.termList, 120, cmd.out]; [ ] _ PO.FindAMinimalCover[StackDecodeRdPLA.termList, 120, cmd.out]; PO.WritePLAFile[ "IFUPLAStackAControl.ttt", cmd.out, StackAControlPLA]; PO.WritePLAFile[ "IFUPLAStackBControl.ttt", cmd.out, StackBControlPLA]; PO.WritePLAFile[ "IFUPLAStackDecode.ttt", cmd.out, StackDecodePLA]; PO.WritePLAFile[ "IFUPLAStackDecodeWtP.ttt", cmd.out, StackDecodeWtPPLA]; PO.WritePLAFile[ "IFUPLAStackDecodeWtL.ttt", cmd.out, StackDecodeWtLPLA]; PO.WritePLAFile[ "IFUPLAStackDecodeRd.ttt", cmd.out, StackDecodeRdPLA]}; Commander.Register[key:"GenStackControl", proc: GenStackControl]; END. κIFUPLAStackControlImpl.mesa Copyright c 1984 by Xerox Corporation. All rights reserved. Last edited by McCreight, April 8, 1986 6:21:16 pm PST Last edited by Curry, September 2, 1986 10:18:11 am PDT StackAControlProc: PROC[argRec: StackAControlIn] RETURNS[resRec: StackAControlOut]; StackBControlProc: PROC[argRec: StackBControlIn] RETURNS[resRec: StackBControlOut]; StackDecodeProc: PROC[argRec: StackDecodeIn] RETURNS[resRec: StackDecodeOut]; This difference corresponds to 11 entries on the stack (since top-bottom = 0 when there is one entry). The iStkNearlyFull signal is used in conjunction with Push2BA to decide whether to convert the target address to the IFU stack overflow handler. Thus there will be exactly 12 frames on the IFU stack when control arrives at the stack overflow handler. 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