DIRECTORY Dragon, PLAOps; IFUPLAInterlock: CEDAR DEFINITIONS = BEGIN InterlockIn: TYPE = RECORD [ -- default must be zero kIsRtOp1: BOOL _ FALSE, -- describes the micro at stage 1B fCtlIsRtOp1: BOOL _ FALSE, cIsField2: BOOL _ FALSE, cIsField3: BOOL _ FALSE, dPCmndIsRd2: BOOL _ FALSE, -- micro at stage 2B generates PBus read a1IsC2: BOOL _ FALSE, a1IsC3: BOOL _ FALSE, b1IsC2: BOOL _ FALSE, b1IsC3: BOOL _ FALSE ]; InterlockOut: TYPE = RECORD [ stage1BHold: BOOL _ FALSE, eUAluLeftSrc1: Dragon.ALULeftSources _ aBus, -- if 1B will advance eUAluRightSrc1: Dragon.ALURightSources _ bBus, eUStore2ASrc1: Dragon.Store2ASources _ bBus, eUSt3AIsCBus1: BOOL _ FALSE ]; END. \IFUPLAInterlock.mesa Copyright c 1984 by Xerox Corporation. All rights reserved. Last edited by Curry, August 27, 1986 7:14:58 pm PDT McCreight, December 19, 1985 4:41:50 pm PST This is BA logic: it computes during PhB using inputs that may be changing during PhB, and its outputs are stable by the end of PhB and can be captured in a PhB latch if necessary. Because its inputs may change during B, it should be implemented either as a static PLA or as an Alps cell. condEffect2: IFUPLAMainPipeControl.CondEffect _ VAL[0], -- for detecting bubble in 2B stage1BHoldIfReject: BOOL _ FALSE, Κ˜šΠbl™Jšœ<™