DIRECTORY
Basics,
Dragon,
DragOpsCross,
IFUPLAInstrDecode,
PLAOps;

IFUPLAInstrDecodeImpl1: CEDAR PROGRAM
IMPORTS IFUPLAInstrDecode, PLAOps EXPORTS IFUPLAInstrDecode =
BEGIN OPEN IFUPLAInstrDecode, PLAOps;

instr, temp:		BoolExpr;
m:			InstrDecodeOut;

DelayedRet:			InstrDecodeOut = [
nextMacro:			hold,
pcNext:				fromPCBus,
microCycleNext:		next, -- so we can recognize first cycle of RET
condEffect0: bubble ];


GenInstrDecodePLA1:  PUBLIC GenInstrDecodePLAProc = {

GenInstrDecodePLAExceptions:  PROC = {
OPEN	DOC: DragOpsCross;
T:		BOOL = TRUE;
all:	Dragon.Byte _ ByteTopSig[8];
BEX:	TYPE = BoolExpr;
ifuSLim:	BEX _ BE[m:[alpha: all], d:[alpha: DOC.ProcessorRegister[ifuSLimit		].ORD]];
ifuYgL:	BEX _ BE[m:[alpha: all], d:[alpha: DOC.ProcessorRegister[ifuYoungestL	].ORD]];
ifuYgPC:	BEX _ BE[m:[alpha: all], d:[alpha: DOC.ProcessorRegister[ifuYoungestPC	].ORD]];
ifuElL:	BEX _ BE[m:[alpha: all], d:[alpha: DOC.ProcessorRegister[ifuEldestL		].ORD]];
ifuElPC:	BEX _ BE[m:[alpha: all], d:[alpha: DOC.ProcessorRegister[ifuEldestPC		].ORD]];

ifuAddr:		BoolExpr	_ BE[m:[alpha:			360B],		d:[alpha:			360B]]; -- last 16

reset:			BoolExpr	_ BE[m:[reset:			TRUE],	d:[reset:				TRUE]];
userMode0:	BoolExpr	_ BE[m:[userMode0:		TRUE],	d:[userMode0:		TRUE]];

pop0ping:		BoolExpr	_ BE[m:[popPending:	TRUE],	d:[popPending:	TRUE]];
push0ing:	BoolExpr	_ BE[m:[pushPending:	TRUE],	d:[pushPending:	TRUE]];
state0:			BoolExpr	_ BE[m:[state: ByteTopSig[8]],		d:[state:			0]];
current0:		BoolExpr	_ state0;


Set[ s: state0,	out: [instStarting0: TRUE] ];


Set[s: reset,	out: [
nextMacro:		hold,
microCycleNext:	next,
protMicroCycle:	TRUE,
pcNext:			fromPCBus,
pcBusSrc:			trapGen,
lSource:			[ zero, zero ],
sSource:			[ l, zero ],
aluOp:			UAdd, -- clears EU carry flag
aReg:				constantZero,
bReg:				constantZero,
flagSrc:			clear ]]; 

current _ BE[m: [reset: TRUE],	d:[reset: FALSE]];

Set[s: current, m:[state: ByteTopSig[8]], d:[state: 112 -- Resetting -- ],	out: [
nextMacro:		hold,
microCycleNext:	next,
protMicroCycle:	TRUE,
pcNext:			fromPCBus,
pcBusSrc:			trapGen,
lSource:			[ zero, zero ],
sSource:			[ l, zero ],
aluOp:			UAdd, -- clears EU carry flag
aReg:				constantZero,
bReg:				constantZero,
flagSrc:			clear ]]; 

Set[s: current, m:[state: ByteTopSig[8]], d:[state: 113 -- Reset finished -- ],		out: [
nextMacro:	jump,
pcNext:		fromPCBus,
pcBusSrc:		pc,
lSource:		[ zero, one ],
sSource:		[ l, zero ],
aluOp:		UAdd, -- clears EU carry flag
aReg:			constantZero,
bReg:			constantZero ]];


Set[s: current, m:[state: ByteTopSig[8]], d:[state: 116 -- trap0 -- ],	out: [
nextMacro:	jump,
pcNext:		fromPCBus,
pcBusSrc:		trapGen,
flagSrc:		clear,
lSource:		[ l3, zero ],
sSource:		[ s3, zero ] ]];


Set[s: current, m:[state: ByteTopSig[8]],d:[state: 120 -- cJump -- ],		out: [
nextMacro:	jump,
pcNext:		fromPCBus,
pcBusSrc:		pipe3,
flagSrc:		lev3,
lSource:		[ l3, zero ],		-- should be 2, but 2 = 3 for cJump
sSource:		[ s2, zero ] ]];	-- S of instr AFTER CJump

Set[s: current, m:[state: ByteTopSig[1]],	d:[state: 128 -- bubble --],		out: Delayed];



current _ And[current, BE[m: [state: ByteTopSig[2]], d:[state: 0]]];
Set[s: current,
m:[instReady: TRUE], d:[instReady: FALSE],		out: Delayed];

current _ And[current, BE[m: [instReady: TRUE], d: [instReady: TRUE]]];

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dRET]]];
Set[s: And[instr,		 Or[pop0ping, push0ing]],					out: [
nextMacro:			hold,
pcNext:				fromPCBus,
microCycleNext:		next, -- so we can recognize first cycle of RET
condEffect0:			bubble]];
Set[s: And[instr,	Not[Or[pop0ping, push0ing]] ],	out: [
nextMacro:			jump,
pcNext:				fromPCBus,
pcBusSrc:				stack,
flagSrc:				stack,
lSource:				[ zero, stack ],
sSource:				[ l, alpha ],
pop0:					TRUE ]];

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dRETN]]];
Set[s: And[instr,		 Or[pop0ping, push0ing]],					out: [
nextMacro:			hold,
pcNext:				fromPCBus,
microCycleNext:		next, -- so we can recognize first cycle of RET
condEffect0:			bubble ]];
Set[s: And[instr,	Not[Or[pop0ping, push0ing]] ],	out: [
nextMacro:			jump,
pcNext:				fromPCBus,
pcBusSrc:				stack,
flagSrc:				stack,
lSource:				[ zero, stack ],
pop0:					TRUE ]];



Set[s:current, m:[op: InstrTopSig[8]], d:[op: dALS],					out:[lSource: [s, alpha]]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dASL],					out:[sSource: [l, alpha]]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dAL],					out:[lSource: [l, alpha]]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dAS],					out:[sSource: [s, alpha]]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dDIS],					out:[popSa: TRUE]];
instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dLIP]]];
Set[s: And[instr,		Not[ifuAddr]],	out: [
bReg:		[ zero, alpha ],
cReg:		[ s, offset, one ],
pushSc:	TRUE ] ];
instr _ And[instr,	ifuAddr];
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 0], out:[
nextMacro:		hold,
pcNext:			fromPCBus,
microCycleNext:	next,
pushSc:			TRUE ] ]; -- aborts if EU stack overflow
Set[s: And[instr, userMode0, state0, ifuElPC], out: [condSel: ModeFault] ];
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 1], out:NoOpMicro];		-- wait
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 2], out:NoOpMicro];		-- wait
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 3], out: [
nextMacro:		hold,
bReg:				fromIfuXBus,
pcNext:			fromPCBus,
microCycleNext:	next,
kIsRtOp0:			TRUE,
cReg:				[ s, offset, zero ] ] ];
instr _ And[instr, BE[m:[state: ByteTopSig[8]], d:[state: 4]]];
Set[s: And[instr, ifuSLim],	out: [x1ASrcSLimit:T											]];
Set[s: And[instr, ifuYgL],	out: [x1ASrcStack:T,								xBusStackL:T	]];
Set[s: And[instr, ifuYgPC],	out: [x1ASrcStack:T												]];
Set[s: And[instr, ifuElL],	out: [x1ASrcStack:T,		xBusStackEldest:T,	xBusStackL:T	]];
Set[s: And[instr, ifuElPC],	out: [x1ASrcStack:T,		xBusStackEldest:T					]];
Set[s: And[instr, ifuYgL],	out: [x1ASrcStackL:T]];
Set[s: And[instr, ifuYgPC],	out: [x1ASrcStackP:T]];
Set[s: And[instr, ifuElL],	out: [x1ASrcStackL:T]];
Set[s: And[instr, ifuElPC],	out: [x1ASrcStackP:T]];

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dSIP]]];
Set[s: And[instr, userMode0, state0], out: [condSel: ModeFault] ]; -- trap if userMode0

Set[s: And[instr,	Not[ifuAddr]], out: [
bReg:		abStackTop,
cReg:		[ zero, alpha ],
popSb:	TRUE ] ];

Set[s: instr,
m: [alpha: ByteTopSig[8]], d: [alpha: DragOpsCross.ProcessorRegister[euField].ORD],
out: [cIsField0: TRUE ] ];

instr _ And[instr,		ifuAddr];
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 0], out:[
nextMacro:		hold,
pcNext:			fromPCBus,
microCycleNext:	next,
bReg:				abStackTop,
popSb:			TRUE,
cReg:				toIfuXBus,
kPadsIn0:			TRUE ] ];
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 1], out:NoOpMicro];		-- wait
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 2], out:NoOpMicro];		-- wait
temp _ And[instr, BE[m:[state: ByteTopSig[8]], d:[state: 3]]];
Set[s: temp, out: NoOpMicro];
Set[s: And[temp, ifuSLim],		out: [x1ADstSLimit:T											]];
Set[s: And[temp, ifuYgL],		out: [x1ADstStack:T,								xBusStackL:T	]];
Set[s: And[temp, ifuYgPC],	out: [x1ADstStack:T												]];
Set[s: And[temp, ifuElL],		out: [x1ADstStack: T,	xBusStackEldest:T,	xBusStackL:T	]];
Set[s: And[temp, ifuElPC],		out: [x1ADstStack:T,		xBusStackEldest:T					]];
Set[s: instr, m:[state: ByteTopSig[8]],	d:[state: 4], out:[ ]]};


GenInstrDecodePLAXfers:  PROC = {
src0:			BoolExpr	_ BE[m:[alpha: 300B],	d:[alpha: 0B]];
src1:			BoolExpr	_ BE[m:[alpha: 300B],	d:[alpha: 100B]];
srTop:			BoolExpr	_ BE[m:[alpha: 200B],	d:[alpha: 200B]];
srPop:			BoolExpr	_ BE[m:[alpha: 300B],	d:[alpha: 300B]];
opt:			BoolExpr	_ BE[m:[alpha: 040B],	d:[alpha: 040B]];
aux:			BoolExpr	_ BE[m:[alpha: 020B],	d:[alpha: 020B]];

m _ [
aReg: abStackTop,
x2ALitSource: alpha,
popSa: TRUE,
aluOp: VSub,
condEffect0: macroJump,
condSel: EZ,
nextMacro: get,
pcPipeSrc: offSetPC ];	-- pcOffSetSrc: betaS
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJEBB],	out:m];
m.condSel _ NE;
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJNEBB],	out:m];

m _ [
aReg: abStackTop,
x2ALitSource: alpha,
popSa: TRUE,
aluOp: VSub,
condEffect0: macroJump,
condSel: EZ,
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: offSetPC, -- pcOffSetSrc: betaS
pcPipeSrc: seqPC
];
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJNEBBJ],	out:m];
m.condSel _ NE;
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJEBBJ],	out:m];

instr _ And[current, BE[m:[op: InstrTopSig[4]], d:[op: dRJEB]]];	-- RJ*B and RJ*BJ
Set[s:current, m:[op: InstrTopSig[5]],	d:[op: dRJEB],	out:[	-- RJ*B
aluOp: VSub,
condSelIsOp57: TRUE,
condEffect0: macroJump,
nextMacro: get,
pcPipeSrc: offSetPC ] ];	-- pcOffSetSrc: betaS
Set[s:current, m:[op: InstrTopSig[5]],	d:[op: dRJEBJ],	out:[	-- RJ*BJ
aluOp: VSub,
condSelIsOp57: TRUE,
condEffect0: macroJump,
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: offSetPC, -- pcOffSetSrc: betaS
pcPipeSrc: seqPC] ];
Set[s: And[		src0,	instr],								out:[aReg:[ cBase, offset, zero ]]];
Set[s: And[		src1,	instr],								out:[aReg:[ cBase, offset, one ]]];
Set[s: And[		srTop,	instr],								out:[aReg:[ s, offset, zero ]]];
Set[s: And[ Not[opt],			aux,	instr],					out:[bReg:[ aBase,	alpha47 ]]];
Set[s: And[ Not[opt],		Not[aux],	instr],					out:[bReg:[ l,			alpha47 ]]];
Set[s: And[opt,	instr],	m:[alpha: 010B], d:[alpha: 000B],	out:[bReg:[ cBase,	alpha47 ]]];
Set[s: And[opt,	instr],	m:[alpha: 004B], d:[alpha: 000B],	out:[bReg:[ cBase,	alpha47 ]]];
Set[s: And[opt,	instr],	m:[alpha: 015B], d:[alpha: 014B],	out:[bReg:[ s, offset, zero	  ]]];
Set[s: And[opt,	instr],	m:[alpha: 015B], d:[alpha: 015B],	out:[bReg:[ s, offset, minus1 ]]];
Set[s: And[srPop,	instr], 									out:[popSa: TRUE]];
Set[s: And[opt,	instr], m:[alpha:	016B],	d:[alpha:	016B],	out:[popSb: TRUE]];

Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJ1],	out: DefaultMicro]; -- to mark as ~Xops
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJ2],	out: DefaultMicro]; -- to mark as ~Xops
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJ3],	out: DefaultMicro]; -- to mark as ~Xops
Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJ5],	out: DefaultMicro]; -- to mark as ~Xops

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dJSR]]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 0], out:[ -- toIfuXBus _ [S]
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
bReg: abStackTop,
cReg: toIfuXBus,
kPadsIn0: TRUE ]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 1], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 2], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 3], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 4], out:[ -- S _ S-1
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: offSetPC, 	-- pcOffSetSrc: xA,
popSa: TRUE ]];

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dJSD]]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 0], out:[
nextMacro:		hold,
pcNext:			fromPCBus,
microCycleNext:	next,
bReg:				abStackTop,
cReg:				toIfuXBus,
kPadsIn0:			TRUE ]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 1], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 2], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 3], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 4], out:[
nextMacro:	jump,
pcNext:		fromPCBus,
pcBusSrc:		x,
popSa:			TRUE ]];

Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJB], out:[
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: offSetPC ]];

Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJDB], out:[
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: offSetPC ]];	-- pcOffSetSrc: alphaBetaS

Set[s:current, m:[op: InstrTopSig[8]],	d:[op: dJQB], out:[
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: alpBetGamDel ]];

Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLFC], out:[
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: offSetPC, 	-- pcOffSetSrc: alphaBetaS,
pcPipeSrc: seqPC,
push0: TRUE ]];

Set[s:current, m:[op: InstrTopSig[8]], d:[op: dDFC], out:[
nextMacro: jump,
pcNext: fromPCBus,
pcBusSrc: alpBetGamDel,
pcPipeSrc: seqPC,
push0: TRUE ]];

Set[s:current, m:[op: InstrTopSig[8]], d:[op: dKFC], out:[
nextMacro:	jump,
pcNext: 		fromPCBus,
pcBusSrc:		xopGen,
pcPipeSrc:	seqPC,
push0:		TRUE,
flagSrc:		clear ]];


instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dSFC]]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 0], out:[ -- toIfuXBus _ [S]
nextMacro:		hold,
pcNext:			fromPCBus,
microCycleNext:	next,
bReg:				abStackTop,
cReg:				toIfuXBus,
kPadsIn0:			TRUE ]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 1], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 2], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 3], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 4], out:[ -- S _ S-1
nextMacro:	jump,
pcNext:		fromPCBus,
pcBusSrc:		x,
pcPipeSrc:	seqPC,
popSa:			TRUE,
push0:		TRUE ]];

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dSFCI]]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 0], out:[ -- toIfuXBus _ [S]^
nextMacro:		hold,
pcNext:			fromPCBus,
microCycleNext:	next,
bReg:				abStackTop,
cReg:				toIfuXBus,
kPadsIn0:			TRUE,
dPCmnd:			Fetch,
dPCmndIsRd0:	TRUE ]];
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 1], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 2], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 3], out:NoOpMicro];	-- wait
Set[s:instr, m:[state: ByteTopSig[8]],	d:[state: 4], out:[ -- S _ S-1
nextMacro:	jump,
pcNext:		fromPCBus,
pcBusSrc:		x,
pcPipeSrc:	seqPC,
push0:		TRUE ]] };

current _ old;
GenInstrDecodePLAExceptions[];
GenInstrDecodePLAXfers[]};

END.


êIFUPLAInstrDecodeImpl1.mesa
Copyright c 1984 by Xerox Corporation.  All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Herrmann, August 14, 1985 12:57:15 pm PDT
Last edited by Curry, September 13, 1986 7:41:31 pm PDT
McCreight, February 27, 1986 3:51:08 pm PST

Set InstStarting bit
Do Exceptions

Note: Reset must be asserted for at least three machine cycles.
Not An Exception

Instruction not ready
Returns must wait for push0 or pop0.  Today (October 25, 1985 11:54:04 am PDT) Russ Atkinson promised to make stack underflow illegal (by altering the PC of the bottom frame to point to a trap handler), so trapping an empty instruction stack is no longer necessary.

instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dRETK]]];
Set[s:	And[instr, userMode0, state0], out: [condSel: ModeFault]]; -- OR it in

Set[s:	And[instr, state0],	out: [
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
bReg:					abStackTop,
cReg:					toIfuXBus,
kPadsIn0:				TRUE,
flagSrc:				stack,
lSource:				[ zero, stack ],
sSource:				[ l, alpha ]] ];
Set[s:	instr,	m:[state: ByteTopSig[8]], d:[state: 1],	out: NoOpMicro];
Set[s:	instr,	m:[state: ByteTopSig[8]], d:[state: 1],	out: [pop0: TRUE]];
... just add it in.  This pop0 logically belongs with state 3, but can be piped ahead because the pop0 doesn't actually happen until three cycles later.  This allows a return following a RETK to proceed without wait states.
Set[s: instr,	m:[state: ByteTopSig[8]], d:[state: 2], out: NoOpMicro];
Set[s: instr,	m:[state: ByteTopSig[8]], d:[state: 3], out: [
nextMacro:			jump,
pcNext:				fromPCBus,
pcBusSrc:				stack,
x1ADstStatus:		TRUE]];
... x1ADstStatus is not pipelined, so it's generated at stage 0B to apply to the destination register address that has reached stage 3B.
Note: We formerly trapped ALS if the stack was empty.  Russ Atkinson now (and has done for some time) guarantees that to be impossible.  EMM October 25, 1985 11:26:44 am PDT.
ALS
Look for the case of a Call - ALS sequence broken by a Reschedule which returns with an empty IStack.  ALS (L_S+alpha) => that the stack is expected to contain some local values which (if IStack is empty) have been swapped out.
instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dALS]] ];
Set[s: And[instr,		pop0ping],										out: Delayed];
Set[s: And[instr,	Not[pop0ping],		empty, Not[push0ing]],	out: Trap];

LIP
check addr to determine if IFU or EU.  EU has no special conditions.
Unfortunately, LIP from an IFU register sometimes has early side effects, including pop0ping the control stack.  Therefore its last microinstruction must not experience any pipeline interference.

OR's in with other bits, protects just LIP IFUEldestPC
Set[s: And[instr, BE[m:[state: ByteTopSig[8]],	d:[state: 3], ifuStat]],
out: [x2ASrcStatus0: TRUE]]; -- add in register-specific bits, on time
Add in register-specific bits, one cycle delayed

SIP


Register-specific bits, to be broadcast in phase 1A
Set[s: And[temp, ifuStat],		out: [x1ADstStatus:T												]];

This final state is necessary because a RET instruction can follow a SIP to IFUYoungestPC or IFUYoungestL, and perhaps in other cases as well.

Used in RR and RJB instructions
dRJ*B and dRJ*BJ  - Bit 4 distinguishes between them
Main Body
AReg
BReg
Stack
�Êj˜š
Ðbl™Jšœ
Ïm
œ1™<Jš
œ8™8Icodeš
œ8™8Jš
œ7™7K™+J™—š
Ïk	˜	Jš
œ˜Jš
œ˜Jš
œ
˜
Jš
œ˜Jš
œ˜J˜—š�Ÿœ
Ÿ˜%JšŸœŸœ˜=JšŸœ
Ÿœ˜%J˜Jš
œ˜Jš
œ˜š
œ ˜ Jš
œ˜Jš
œ˜JšœÏbœÏc)˜@Jš
œ˜J˜—J˜—šœŸœ˜5J˜šÏnœŸœ˜&JšŸœ
Ÿœ˜Jš¢
œŸœŸœ
˜Jš
œ!˜!JšŸœŸœ˜Jš	œ	ŸœŸœŸœ Ÿœ˜UJš	œŸœŸœŸœ"Ÿœ˜VJš	œ	ŸœŸœŸœ#Ÿœ˜XJš	œŸœŸœŸœ!Ÿœ˜UJš	œ	ŸœŸœŸœ"Ÿœ˜WJ˜JšœŸœ)¡
˜JJ˜JšœŸœ
ŸœŸœ˜>JšœŸœŸœŸœ˜EJ˜JšœŸœŸœŸœ˜EJšœŸœŸœŸœ˜FJšœŸœ,˜CJ˜J˜Jš
 ™J˜Jšœ%Ÿœ˜-J˜Jš
 
™
J™Jš
œ?™?J˜š
œ˜Jš
œ˜Jš
œ˜JšœŸœ
˜Jš
œ˜Jš
œ˜J˜Jš
œ˜Jšœ¡˜&Jš
œ˜Jš
œ˜Jš
œ˜J˜—Jš œŸœŸœ
Ÿœ˜1J˜šœ8¡œ
˜QJš
œ˜Jš
œ˜JšœŸœ
˜Jš
œ˜Jš
œ˜J˜Jš
œ˜Jšœ¡˜&Jš
œ˜Jš
œ˜Jš
œ˜J˜—šœ8¡œ˜WJš
œ˜Jš
œ˜Jš
œ˜J˜Jš
œ˜Jšœ¡˜%Jš
œ˜Jš
œ˜J˜J˜—šœ8¡œ
˜MJš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜—J˜J˜šœ7¡œ˜MJš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jšœ¡#˜<Jšœ¡Ðbc¡˜4—J˜Jšœ8¡œ˜VJ˜J˜—š
�™J˜Jš œŸœ+˜DJ™Jš
 ™š
œ˜JšœŸœŸœ˜:J˜—Jš œŸœŸœŸœ˜GJ˜Jš
œ‰™‰J™JšœŸœ  œ˜?š
œ7˜7Jš
œ˜Jš
œ˜Jšœ œ¡)˜@Jš
œ˜—š
œ7˜7Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jšœ
Ÿœ˜—J˜JšœŸœ  œ˜@š
œ7˜7Jš
œ˜Jš
œ˜Jšœ œ¡)˜@Jš
œ˜—šœ-¡
œ	˜7Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jšœ
Ÿœ˜—J˜JšœŸœ  œ™@JšœB¡™MJ™šœ 
œ	™!Jš
œ™Jš
œ™Jš
œ™Jš
œ™Jš
œ™Jšœ
Ÿœ
™Jš
œ™Jš
œ™Jš
œ™—Jšœ2 
œ™Fšœ2 
œŸœ™IJš
ϧ
™ß
—Jšœ2 
œ™Fšœ2 
œ	™<Jš
œ™Jš
œ™Jš
œ™JšœŸœ™Jš
œˆ
™ˆ
—J˜š œ©
™®
Jš œä
™ç
JšœŸœ  
Ðbfœ™@Jš
œ5™5Jš
œD™D—J˜Jšœ. œ"˜TJšœ. œ"˜TJšœ. œ"˜SJšœ. œ"˜SJšœ. œŸœ˜LJ™Jš œ‰™ŒJšœŸœ  œ˜?š
œ(˜(Jš
œ˜Jš
œ˜JšœŸœ˜—Jš
œ˜J™šœ2 
œ˜;Jš
œ˜Jš
œ˜Jš
œ˜Jšœ
Ÿœ¡˜2—šœ 	œ
 œ 	œ˜KJš
œ6™6—Jšœ2 
œ¡˜NJšœ2 
œ¡˜Nšœ2 
œ	˜<Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜JšœŸœ
˜Jš
œ!˜!—šœŸœ% 
œ
™GJšœŸœ¡)™F—Jš
œ0™0JšœŸœ*˜?Jš
œ>˜>Jš
œG˜GJš
œ>˜>Jš
œT˜TJš
œK˜KJš
œ2˜2Jš
œ3˜3Jš
œ2˜2Jš
œ3˜3J˜J™Jš
 ™Jš œŸœ  œ˜?šœC¡˜WJ˜—š
œ'˜'Jš
œ˜Jš
œ˜JšœŸœ˜J˜—š
œ
˜
JšœNŸœ˜SJšœŸœ˜J˜—Jš
œ˜J™šœ2 
œ˜;Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jšœ	Ÿœ
˜Jš
œ˜JšœŸœ˜—Jšœ2 
œ¡˜NJšœ2 
œ¡˜NJšœŸœ% 
œ˜>Jš
œ˜J™Jš
œ3™3Jš
œ?™?Jš
œ>˜>Jš
œG˜GJš
œ=˜=Jš
œT˜TJš
œK˜KJ™Jš
¡Ž
™Ž
Jšœ2 
œ
˜@—J˜J˜š¢œŸœ˜!J™Jš
œ™JšœŸœ!˜6JšœŸœ#˜8JšœŸœ#˜9JšœŸœ#˜9JšœŸœ#˜7JšœŸœ#˜7J˜˜Jš
œ˜Jš
œ˜JšœŸœ
˜Jš
œ˜J˜Jšœ	Ÿœ
˜Jš
œ˜Jšœ¡˜,—š
œ=˜=JšœŸœ
˜—Jš
œ>˜>J˜˜Jš
œ˜Jš
œ˜JšœŸœ
˜Jš
œ˜J˜Jšœ	Ÿœ
˜Jš
œ˜Jš
œ˜Jšœ¡˜)Jš
œ˜Jš
œ˜—š
œ?˜?JšœŸœ
˜—Jš
œ>˜>J˜Jš œ$™4JšœŸœ  œ¡˜Rš
 	™	šœ. œ	¡£˜CJš
œ˜JšœŸœ
˜Jš
œ˜Jš
œ˜Jšœ¡˜.—šœ. œ	¡£˜EJš
œ˜JšœŸœ
˜J˜Jš
œ˜Jš
œ˜Jšœ¡˜)Jš
œ˜——š
 ™Jš
œF˜FJš
œE˜EJš
œC˜C—š
 ™Jš
œH˜HJš
œJ˜JJš
œY˜YJš
œY˜YJš
œ\˜\Jš
œ\˜\—š
 ™Jšœ/Ÿœ˜6JšœFŸœ˜M—J˜Jšœ. œ¡˜[Jšœ. œ¡˜[Jšœ. œ¡˜[Jšœ. œ¡˜[J˜Jš œŸœ  œ˜?šœ;¡˜MJš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jšœ
Ÿœ˜—JšœE¡˜LJšœE¡˜LJšœE¡˜Lšœ:¡˜EJš
œ˜Jš
œ˜Jšœ¡˜(JšœŸœ˜—J˜Jš œŸœ  œ˜?š
œ:˜:Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜JšœŸœ˜—JšœE¡˜LJšœE¡˜LJšœE¡˜Lš
œ:˜:Jš
œ˜Jš
œ˜Jš
œ
˜
Jšœ	Ÿœ˜—J˜šœ. œ˜9Jš
œ˜Jš
œ˜Jš
œ˜—J˜šœ. œ˜:Jš
œ˜Jš
œ˜Jšœ¡œ
˜1—J˜šœ. œ˜:Jš
œ˜Jš
œ˜Jš
œ˜—J˜šœ. œ˜:Jš
œ˜Jš
œ˜Jšœ¡˜0Jš
œ˜JšœŸœ˜—J˜šœ. œ˜:Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜JšœŸœ˜—J˜šœ. œ˜:Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜JšœŸœ
˜
Jš
œ˜—J˜J˜JšœŸœ  œ˜?šœ1 
œ	¡˜MJš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jšœ	Ÿœ˜—Jšœ1 
œ¡˜LJšœ1 
œ¡˜LJšœ1 
œ¡˜Lšœ1 
œ¡˜EJš
œ˜Jš
œ˜Jš
œ
˜
Jš
œ˜Jšœ	Ÿœ
˜JšœŸœ˜—J˜Jš œŸœ  œ˜@šœ1 
œ	¡˜NJš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜Jš
œ˜JšœŸœ
˜Jš
œ˜Jšœ
Ÿœ˜—Jšœ1 
œ¡˜LJšœ1 
œ¡˜LJšœ1 
œ¡˜Lšœ1 
œ¡˜EJš
œ˜Jš
œ˜Jš
œ
˜
Jš
œ˜JšœŸœ˜—J˜Jš
œ˜Jš
œ˜Jš
œ˜—J˜JšŸœ
˜˜J˜———…—5^Q²