DIRECTORY
DragOpsCross,
IFUPLA,
PLAOps;

IFUPLAImplB3: CEDAR PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;

GeneratePhBPLA3:  PUBLIC PROC = {
sglBiAlu:		PO.BoolExpr	_ 			BE[m:[alpha:351B], d:[alpha:100B]];
sglUnAlu:	PO.BoolExpr	_ PO.Or[	BE[m:[alpha:351B], d:[alpha:110B]],
											BE[m:[alpha:371B], d:[alpha:160B]],
											BE[m:[alpha:375B], d:[alpha:170B]]];
dblUnAlu:	PO.BoolExpr	_ PO.Or[	BE[m:[alpha:351B], d:[alpha:111B]],
											BE[m:[alpha:371B], d:[alpha:161B]]];
dblBiAlu:		PO.BoolExpr	_ 			BE[m:[alpha:351B], d:[alpha:101B]];
sglBiCom:		PO.BoolExpr	_ 			BE[m:[alpha:371B], d:[alpha:140B]];
dblBiCom:	PO.BoolExpr	_ 			BE[m:[alpha:371B], d:[alpha:141B]];
sglUnCom:	PO.BoolExpr	_ 			BE[m:[alpha:371B], d:[alpha:150B]];
dblUnCom:	PO.BoolExpr	_ 			BE[m:[alpha:371B], d:[alpha:151B]];
sglUnCvt:	PO.BoolExpr	_ PO.Or[	BE[m:[alpha:373B], d:[alpha:173B]],
											BE[m:[alpha:375B], d:[alpha:174B]]];
dblUnCvt:	PO.BoolExpr	_ 			BE[m:[alpha:373B], d:[alpha:171B]];
sglBiMult:	PO.BoolExpr	_ 			BE[m:[alpha:301B], d:[alpha:200B]];
dblBiMult:	PO.BoolExpr	_ 			BE[m:[alpha:301B], d:[alpha:201B]];
setMode:		PO.BoolExpr	_ 			BE[m:[alpha:300B], d:[alpha:300B]];
instr:			PO.BoolExpr;
state:			PO.BoolExpr;
m:				MicroInst;

GeneratePhBPLA3a:  PROC = {
instr _ PO.And[current,	BE[m:[op: instrIsSig], d:[op: dFP]]];
state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 0]]];
m _ [
dontGetNextMacro:	TRUE,
xBSource:				pc,
euPBusCmd:			StoreFP];	
m.kASource	_ fpLdMode;		Set[s: PO.And[setMode,		state],  out:m];
m.bReg		_ [s, zero];
m.kASource	_ fpLdAMsw; 	Set[s: PO.And[sglUnCom,	state], out:m];
m.kASource	_ fpLdAMsw; 	Set[s: PO.And[sglUnAlu,	state], out:m];
m.kASource	_ fpLdAMsw; 	Set[s: PO.And[sglUnCvt,	state], out:m];
m.kASource	_ fpLdALsw; 	Set[s: PO.And[dblUnCom,	state], out:m];
m.kASource	_ fpLdALsw; 	Set[s: PO.And[dblUnAlu,	state], out:m];
m.kASource	_ fpLdALsw; 	Set[s: PO.And[dblUnCvt,	state], out:m];
m.kASource	_ fpLdBMsw; 	Set[s: PO.And[sglBiCom,	state], out:m];
m.kASource	_ fpLdBMsw; 	Set[s: PO.And[sglBiAlu,		state], out:m];
m.kASource	_ fpLdBMsw; 	Set[s: PO.And[sglBiMult,	state], out:m];
m.kASource	_ fpLdBLsw; 	Set[s: PO.And[dblBiCom,	state], out:m];
m.kASource	_ fpLdBLsw; 	Set[s: PO.And[dblBiAlu,	state], out:m];
m.kASource	_ fpLdBLsw; 	Set[s: PO.And[dblBiMult,	state], out:m];


state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 1]]];
m _ [dontGetNextMacro: FALSE];	Set[s: PO.And[setMode,		state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnCvt,	state], out:m];
m _ [
dontGetNextMacro: TRUE,
xBSource: pc,
bReg: [s, minus1],
euPBusCmd: StoreFP];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[dblUnCom,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[dblUnAlu,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[dblUnCvt,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[sglBiCom,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[sglBiAlu,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[sglBiMult,	state], out:m];
m.kASource _ fpLdBMsw; 		Set[s: PO.And[dblBiCom,	state], out:m];
m.kASource _ fpLdBMsw; 		Set[s: PO.And[dblBiAlu,	state], out:m];
m.kASource _ fpLdBMsw; 		Set[s: PO.And[dblBiMult,	state], out:m];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 2]]];
m _ NoOpMicro;					Set[s: PO.And[sglUnCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnCvt,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnCvt,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiMult,	state], out:m];
m _ [
dontGetNextMacro: TRUE,
xBSource:			pc,
bReg:				[  s, minus2 ],
euPBusCmd:		StoreFP ];
m.kASource _ fpLdALsw; 			Set[s: PO.And[dblBiCom,	state], out:m];
m.kASource _ fpLdALsw; 			Set[s: PO.And[dblBiAlu,	state], out:m];
m.kASource _ fpLdALsw; 			Set[s: PO.And[dblBiMult,	state], out:m];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 3]]];
m _ NoOpMicro;					Set[s: PO.And[sglUnCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglUnCvt,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnCvt,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiMult,	state], out:m];
m _ [
dontGetNextMacro: TRUE,
xBSource:			pc,
bReg:				[  s, minus3 ],
euPBusCmd:		StoreFP ];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[dblBiCom,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[dblBiAlu,	state], out:m];
m.kASource _ fpLdAMsw; 		Set[s: PO.And[dblBiMult,	state], out:m] };



GeneratePhBPLA3b: PROC = {
state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 4]]];
Set[s: PO.And[sglUnCom,	state], out:[
dontGetNextMacro: FALSE,
deltaSa:			pop,
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
Set[s: PO.And[sglUnAlu,	state], out:[
dontGetNextMacro: FALSE,
cReg:				[  s, zero ],
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
Set[s: PO.And[sglUnCvt,	state], out:[
dontGetNextMacro: TRUE,
xBSource:			pc,
cReg:				[  s, zero ],
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
m _ NoOpMicro;					Set[s: PO.And[dblUnCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblUnCvt,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[sglBiMult,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiMult,	state], out:m];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 5]]];
Set[s: PO.And[sglUnCvt,	state], out:[
dontGetNextMacro: FALSE,
deltaSc:			push,
cReg:				[  s,  one ],
kASource:		fpUnldLsw,
euPBusCmd:		FetchFPAlu ]];
m _ [
dontGetNextMacro: FALSE,
deltaSa:			pop,
deltaSb:			pop,
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ];
Set[s: PO.And[dblUnCom,	state], out:m];
Set[s: PO.And[sglBiCom,	state], out:m];
Set[s: PO.And[dblUnAlu,	state], out:[
dontGetNextMacro: TRUE,
xBSource:			pc,
cReg:				[  s, minus1 ],
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
m _ [
dontGetNextMacro: FALSE,
deltaSa:			pop,
cReg:				[  s, minus1 ],
kASource:		fpUnldMsw,

euPBusCmd:		FetchFPAlu ];
Set[s: PO.And[dblUnCvt,	state], out:m];
Set[s: PO.And[sglBiAlu,	state], out:m];
Set[s: PO.And[sglBiMult,	state], out:[
dontGetNextMacro: FALSE,
deltaSa:			pop,
cReg:				[  s, minus1 ],
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPMult ]];
m _ NoOpMicro;					Set[s: PO.And[dblBiCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiMult,	state], out:m];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 6]]];
Set[s: PO.And[dblUnAlu,	state], out:[
dontGetNextMacro: FALSE,
cReg:				[  s, zero ],
kASource:		fpUnldLsw,
euPBusCmd:		FetchFPAlu ]];
m _ NoOpMicro;					Set[s: PO.And[dblBiCom,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiAlu,	state], out:m];
m _ NoOpMicro;					Set[s: PO.And[dblBiMult,	state], out:m];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 7]]];
Set[s: PO.And[dblBiCom,	state], out:[
dontGetNextMacro: TRUE,
xBSource:			pc,
deltaSa:			pop,
deltaSb:			pop,   --  Two more left for next cycle
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
Set[s: PO.And[dblBiAlu,	state], out:[
dontGetNextMacro: TRUE,
xBSource:			pc,
cReg:				[  s, minus3 ],
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
m _ NoOpMicro;					Set[s: PO.And[dblBiMult,	state], out:m];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 8]]];
Set[s: PO.And[dblBiCom,	state], out:[
dontGetNextMacro: FALSE,
deltaSa:			pop,
deltaSb:			pop,   --  Last two
kASource:		fpUnldMsw,
euPBusCmd:		FetchFPAlu ]];
Set[s: PO.And[dblBiAlu,	state], out:[
dontGetNextMacro: FALSE,
deltaSa:			pop,
deltaSb:			pop,
cReg:				[  s, minus2 ],
kASource:		fpUnldLsw,
euPBusCmd:		FetchFPAlu ]];
Set[s: PO.And[dblBiMult,	state], out:[
dontGetNextMacro: FALSE,
deltaSa:			pop,
deltaSb:			pop,
cReg:				[  s, minus2 ],
kASource:		fpUnldLsw,
euPBusCmd:		FetchFPAlu ]];

state _ PO.And[instr,		BE[m:[state: byteIsSig], d:[state: 9]]];
Set[s: PO.And[dblBiMult,	state], out:[
dontGetNextMacro: FALSE,
deltaSa:			pop,
deltaSb:			pop,
cReg:				[  s, minus2 ],
kASource:		fpUnldLsw,
euPBusCmd:		FetchFPMult ]]};

GeneratePhBPLA3a[];
GeneratePhBPLA3b[];
GeneratePhBPLA4[] };

END.


ÆIFUPLAImplB3.mesa
Copyright c 1984 by Xerox Corporation.  All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Curry, November 4, 1984 1:31:45 pm PST


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