IFUPLAStackControlImpl.mesa
Copyright c 1984 by Xerox Corporation. All rights reserved.
Last edited by McCreight, April 8, 1986 6:21:16 pm PST
Last edited by Curry, June 9, 1986 10:45:26 am PDT
DIRECTORY
Commander,
IFUPLAStackControl,
IO,
PLAOps;
IFUPLAStackControlImpl:
CEDAR
PROGRAM
IMPORTS Commander, IO, PLAOps =
BEGIN OPEN PO: PLAOps;
StackDecodeIn: TYPE = IFUPLAStackControl.StackDecodeIn;
StackAControlIn: TYPE = IFUPLAStackControl.StackAControlIn;
StackBControlIn: TYPE = IFUPLAStackControl.StackBControlIn;
StackAControlOut: TYPE = IFUPLAStackControl.StackAControlOut;
StackBControlOut: TYPE = IFUPLAStackControl.StackBControlOut;
StackDecodeOut: TYPE = IFUPLAStackControl.StackDecodeOut;
StackDecodeWtPOut: TYPE = IFUPLAStackControl.StackDecodeWtPOut;
StackDecodeWtLOut: TYPE = IFUPLAStackControl.StackDecodeWtLOut;
StackDecodeRdOut: TYPE = IFUPLAStackControl.StackDecodeRdOut;
Index: TYPE = IFUPLAStackControl.Index;
SixteenBits: TYPE = IFUPLAStackControl.SixteenBits;
TosMod: Index = IFUPLAStackControl.TosMod;
BosMod: Index = IFUPLAStackControl.BosMod;
DiffSig: Index = IFUPLAStackControl.DiffSig;
TosSig: Index = IFUPLAStackControl.TosSig;
BosSig: Index = IFUPLAStackControl.BosSig;
StackAControlPLA: PUBLIC PLAOps.PLA;
StackBControlPLA: PUBLIC PLAOps.PLA;
StackDecodePLA: PUBLIC PLAOps.PLA;
StackDecodeWtPPLA: PUBLIC PLAOps.PLA;
StackDecodeWtLPLA: PUBLIC PLAOps.PLA;
StackDecodeRdPLA: PUBLIC PLAOps.PLA;
StackAControlProc: PROC[argRec: StackAControlIn] RETURNS[resRec: StackAControlOut];
StackBControlProc: PROC[argRec: StackBControlIn] RETURNS[resRec: StackBControlOut];
StackDecodeProc: PROC[argRec: StackDecodeIn] RETURNS[resRec: StackDecodeOut];
nearlyFullDiff: Index = 10;
This difference corresponds to 11 entries on the stack (since top-bottom = 0 when there is one entry). The iStkNearlyFull signal is used in conjunction with Push2BA to decide whether to convert the target address to the IFU stack overflow handler. Thus there will be exactly 12 frames on the IFU stack when control arrives at the stack overflow handler.
GenStackAControlPLA:
PROC = {
SetA[out:[stackAdjTos: TRUE], s: PO.Or[push3, pop3] ];
SetA[out:[stackAddendIsOnes:
TRUE],
s: PO.Or[pop3, PO.And[x1ADstStack, xBusStackEldest, PO.Not[ xBusStackL]]] ];
SetA[out:[stackCarryIsOne:
TRUE],
s: PO.Or[push3, PO.And[x1ASrcStack, xBusStackEldest, PO.Not[ xBusStackL]]] ]};
GenStackBControlPLA:
PROC = {
SetB[ out:[push3: TRUE], m:[push3: TRUE], d:[push3: TRUE] ];
SetB[ out:[pop3: TRUE], m:[pop3: TRUE], d:[pop3: TRUE] ];
SetB[out:[iStkNearlyFull:
TRUE],
s: PO.And[push3, BEB[m:[stackDiff: DiffSig], d:[stackDiff: nearlyFullDiff-1]]] ];
SetB[out:[iStkNearlyFull:
TRUE],
s: PO.And[PO.Not[pop3], BEB[m:[stackDiff: DiffSig], d:[stackDiff: nearlyFullDiff]]] ];
FOR diff: Index
IN (nearlyFullDiff..TosMod)
DO
SetB[out:[iStkNearlyFull: TRUE], m:[stackDiff: DiffSig], d:[stackDiff: diff] ];
ENDLOOP };
GenStackDecodePLA:
PROC = {
out: SixteenBits ← 1;
current, temp: PO.BoolExpr;
WtP
out ← 1;
temp ← PO.And[PO.Not[x1ADstStack], push3];
FOR val: Index
DECREASING
IN [0..TosMod)
DO
tos: Index ← (val-1+TosMod) MOD TosMod; -- writes above top of stack
SetDec[out:[stkLdP: out], s: temp, m:[tos: TosSig], d:[tos: tos] ];
out ← out*2 ENDLOOP;
current ← PO.Not[temp];
temp ← PO.And[x1ADstStack, PO.Not[xBusStackL], xBusStackEldest];
out ← 1;
FOR val: Index
DECREASING
IN [0..BosMod)
DO
bos: Index ← (val+1) MOD BosMod; -- writes below bottom of stack
SetDec[out:[stkLdP: out], s: PO.And[current, temp], m:[bos: BosSig], d:[bos: bos] ];
out ← out*2 ENDLOOP;
current ← PO.And[current, PO.Not[temp]];
temp ← PO.And[x1ADstStack, PO.Not[xBusStackL], PO.Not[xBusStackEldest]];
out ← 1;
FOR val: Index
DECREASING
IN [0..TosMod)
DO
SetDec[out:[stkLdP: out], s: PO.And[current, temp], m:[tos: TosSig], d:[tos: val] ];
out ← out*2 ENDLOOP;
WtL
out ← 1;
temp ← PO.And[PO.Not[x1ADstStack], push3];
FOR val: Index
DECREASING
IN [0..TosMod)
DO
tos: Index ← (val-1+TosMod) MOD TosMod; -- write above top of stack
SetDec[out:[stkLdL: out], s: temp, m:[tos: TosSig], d:[tos: tos] ];
out ← out*2 ENDLOOP;
current ← PO.Not[temp];
temp ← PO.And[x1ADstStack, xBusStackL, xBusStackEldest];
out ← 1;
FOR val: Index
DECREASING
IN [0..BosMod)
DO
SetDec[out:[stkLdL: out], s: PO.And[current, temp], m:[bos: BosSig], d:[bos: val] ];
out ← out*2 ENDLOOP;
current ← PO.And[current, PO.Not[temp]];
temp ← PO.And[x1ADstStack, xBusStackL, PO.Not[xBusStackEldest]];
out ← 1;
FOR val: Index
DECREASING
IN [0..TosMod)
DO
SetDec[out:[stkLdL: out], s: PO.And[current, temp], m:[tos: TosSig], d:[tos: val] ];
out ← out*2 ENDLOOP;
Rd
out ← 1;
temp ← PO.Or[
PO.And[PO.Not[x1ASrcStack], PO.Not[pop3]],
PO.And[x1ASrcStack, PO.Not[xBusStackEldest]]];
This temp was changed to the one below to remove one of the four terms
temp ← PO.And[PO.Not[xBusStackEldest], PO.Not[pop3]];
FOR val: Index
DECREASING
IN [0..TosMod)
DO
SetDec[out:[stkRd: out], s: temp, m:[tos: TosSig], d:[tos: val] ];
out ← out*2 ENDLOOP;
current ← PO.Not[temp];
temp ← PO.And[PO.Not[x1ASrcStack], pop3];
out ← 1;
FOR val: Index
DECREASING
IN [0..TosMod)
DO
tos: Index ← (val+1) MOD TosMod;
SetDec[out:[stkRd: out], s: PO.And[current, temp], m:[tos: TosSig], d:[tos: tos] ];
out ← out*2 ENDLOOP;
current ← PO.And[current, PO.Not[temp]];
temp ← PO.And[x1ASrcStack, xBusStackEldest];
out ← 1;
FOR val: Index
DECREASING
IN [0..BosMod)
DO
SetDec[out:[stkRd: out], s: PO.And[current, temp], m:[bos: BosSig], d:[bos: val] ];
out ← out*2 ENDLOOP };
BEA:
PROC [m, d: StackAControlIn]
RETURNS[
PO.BoolExpr] = {
mRef: REF StackAControlIn ← NARROW[StackAControlPLA.mask];
dRef: REF StackAControlIn ← NARROW[StackAControlPLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PO.GetBEForDataMask[StackAControlPLA]]};
BEB:
PROC [m, d: StackBControlIn]
RETURNS[
PO.BoolExpr] = {
mRef: REF StackBControlIn ← NARROW[StackBControlPLA.mask];
dRef: REF StackBControlIn ← NARROW[StackBControlPLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PO.GetBEForDataMask[StackBControlPLA]]};
BEDEC:
PROC [m, d: StackDecodeIn]
RETURNS[
PO.BoolExpr] = {
mRef: REF StackDecodeIn ← NARROW[StackDecodePLA.mask];
dRef: REF StackDecodeIn ← NARROW[StackDecodePLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PO.GetBEForDataMask[StackDecodePLA]]}; -- only ins import
SetA:
PROC [s:
PO.BoolExpr ←
NIL, m, d: StackAControlIn ← [ ], out: StackAControlOut] = {
res: REF StackAControlOut ← NARROW[StackAControlPLA.out];
IF s=
NIL
THEN s ← BEA[m,d]
ELSE s ← PO.And[s, BEA[m,d] ];
res^ ← out; PO.SetOutForBE[StackAControlPLA, s]};
SetB:
PROC [s:
PO.BoolExpr ←
NIL, m, d: StackBControlIn ← [ ], out: StackBControlOut] = {
res: REF StackBControlOut ← NARROW[StackBControlPLA.out];
IF s=
NIL
THEN s ← BEB[m,d]
ELSE s ← PO.And[s, BEB[m,d] ];
res^ ← out; PO.SetOutForBE[StackBControlPLA, s]};
SetDec:
PROC [s:
PO.BoolExpr ←
NIL, m, d: StackDecodeIn ← [ ], out: StackDecodeOut] = {
res: REF StackDecodeOut ← NARROW[StackDecodePLA.out];
resWtP: REF StackDecodeWtPOut ← NARROW[StackDecodeWtPPLA.out];
resWtL: REF StackDecodeWtLOut ← NARROW[StackDecodeWtLPLA.out];
resRd: REF StackDecodeRdOut ← NARROW[StackDecodeRdPLA.out];
s ← IF s=NIL THEN BEDEC[m,d] ELSE PO.And[ s, BEDEC[m,d] ];
res^ ← out; PO.SetOutForBE[StackDecodePLA, s];
IF out.stkLdP#0 THEN {resWtP.stkLdP ← out.stkLdP; PO.SetOutForBE[StackDecodeWtPPLA, s]};
IF out.stkLdL#0 THEN {resWtL.stkLdL ← out.stkLdL; PO.SetOutForBE[StackDecodeWtLPLA, s]};
IF out.stkRd#0 THEN {resRd.stkRd ← out.stkRd; PO.SetOutForBE[StackDecodeRdPLA, s]}};
x1ASrcStack: PO.BoolExpr;
x1ADstStack: PO.BoolExpr;
xBusStackEldest: PO.BoolExpr;
xBusStackL: PO.BoolExpr;
push3: PO.BoolExpr;
pop3: PO.BoolExpr;
GenStackControl: Commander.CommandProc = {
inTypeA: IO.ROPE ← "IFUPLAStackControl.StackAControlIn";
inTypeB: IO.ROPE ← "IFUPLAStackControl.StackBControlIn";
inTypeDec: IO.ROPE ← "IFUPLAStackControl.StackDecodeIn";
StackAControlPLA ← PO.NewPLA[inTypeA, "IFUPLAStackControl.StackAControlOut"];
StackBControlPLA ← PO.NewPLA[inTypeB, "IFUPLAStackControl.StackBControlOut"];
StackDecodePLA ← PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeOut"];
StackDecodeWtPPLA ← PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeWtPOut"];
StackDecodeWtLPLA ← PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeWtLOut"];
StackDecodeRdPLA ← PO.NewPLA[inTypeDec, "IFUPLAStackControl.StackDecodeRdOut"];
x1ASrcStack ← BEA[m:[x1ASrcStack: TRUE], d:[x1ASrcStack: TRUE]];
x1ADstStack ← BEA[m:[x1ADstStack: TRUE], d:[x1ADstStack: TRUE]];
xBusStackEldest ← BEA[m:[xBusStackEldest: TRUE], d:[xBusStackEldest: TRUE]];
xBusStackL ← BEA[m:[xBusStackL: TRUE], d:[xBusStackL: TRUE]];
push3 ← BEA[m:[push3: TRUE], d:[push3: TRUE]];
pop3 ← BEA[m:[pop3: TRUE], d:[pop3: TRUE]];
GenStackAControlPLA [];
push3 ← BEB[m:[push3: TRUE], d:[push3: TRUE]];
pop3 ← BEB[m:[pop3: TRUE], d:[pop3: TRUE]];
GenStackBControlPLA [];
x1ASrcStack ← BEDEC[m:[x1ASrcStack: TRUE], d:[x1ASrcStack: TRUE]];
x1ADstStack ← BEDEC[m:[x1ADstStack: TRUE], d:[x1ADstStack: TRUE]];
xBusStackEldest ← BEDEC[m:[xBusStackEldest: TRUE], d:[xBusStackEldest: TRUE]];
xBusStackL ← BEDEC[m:[xBusStackL: TRUE], d:[xBusStackL: TRUE]];
push3 ← BEDEC[m:[push3: TRUE], d:[push3: TRUE]];
pop3 ← BEDEC[m:[pop3: TRUE], d:[pop3: TRUE]];
GenStackDecodePLA [];
[ ] ← PO.ConvertTermListToCompleteSum[StackAControlPLA.termList, FALSE,FALSE,cmd.out];
[ ] ← PO.ConvertTermListToCompleteSum[StackBControlPLA.termList, FALSE,FALSE,cmd.out];
[ ] ← PO.ConvertTermListToCompleteSum[StackDecodePLA.termList, FALSE,FALSE,cmd.out];
[ ] ← PO.ConvertTermListToCompleteSum[StackDecodeWtPPLA.termList, FALSE,FALSE,cmd.out];
[ ] ← PO.ConvertTermListToCompleteSum[StackDecodeWtLPLA.termList, FALSE,FALSE,cmd.out];
[ ] ← PO.ConvertTermListToCompleteSum[StackDecodeRdPLA.termList, FALSE,FALSE,cmd.out];
[ ] ← PO.FindAMinimalCover[StackAControlPLA.termList, 120, cmd.out];
[ ] ← PO.FindAMinimalCover[StackBControlPLA.termList, 120, cmd.out];
[ ] ← PO.FindAMinimalCover[StackDecodePLA.termList, 120, cmd.out];
[ ] ← PO.FindAMinimalCover[StackDecodeWtPPLA.termList, 120, cmd.out];
[ ] ← PO.FindAMinimalCover[StackDecodeWtLPLA.termList, 120, cmd.out];
[ ] ← PO.FindAMinimalCover[StackDecodeRdPLA.termList, 120, cmd.out];
PO.WritePLAFile[ "IFUPLAStackAControl.ttt", cmd.out, StackAControlPLA];
PO.WritePLAFile[ "IFUPLAStackBControl.ttt", cmd.out, StackBControlPLA];
PO.WritePLAFile[ "IFUPLAStackDecode.ttt", cmd.out, StackDecodePLA];
PO.WritePLAFile[ "IFUPLAStackDecodeWtP.ttt", cmd.out, StackDecodeWtPPLA];
PO.WritePLAFile[ "IFUPLAStackDecodeWtL.ttt", cmd.out, StackDecodeWtLPLA];
PO.WritePLAFile[ "IFUPLAStackDecodeRd.ttt", cmd.out, StackDecodeRdPLA]};
Commander.Register[key:"GenStackControl", proc: GenStackControl];
END.