GenPhBOutputs:
PROC = {
maskableTrap:
PO.BoolExpr ←
PO.And[
BETrue[[trapsEnbled2: TRUE]],
PO.Or[
BETrue[[eStkOverflow2: TRUE]],
PO.And[
BETrue[[instStarting2: TRUE]],
BETrue[[rschWaiting2: TRUE]] ],
PO.And[
BETrue[[push2: TRUE]],
BETrue[[iStkNearlyFull: TRUE]] ] ] ];
stage2Failed:
PO.BoolExpr ←
PO.Or[
BETrue[[reset: TRUE]],
BETrue[[stage2BAbort: TRUE]],
PO.And[
BETrue[[eUCondition2: TRUE]],
BE[m:[condEffect2: condEffectIsSig], d:[condEffect2: macroTrap]] ],
maskableTrap ];
stage2FailedOr1Hold:
PO.BoolExpr ←
PO.Or[
stage2Failed,
BETrue[[stage1BHold: TRUE]] ];
loadStage1: PO.BoolExpr ← BEFalse[[microExcptJmpBubble: TRUE]];
loadStages23:
PO.BoolExpr ←
PO.Or[ BEFalse[[dPReject: TRUE]], BETrue[[reset: TRUE]] ];
Set[ s: stage2Failed, out: [stage3A: abort ] ];
Set[ s: stage2FailedOr1Hold, out: [stage2A: bubble ] ];
Set[ s: loadStage1, out: [loadStage1: TRUE ] ];
Set[ s: loadStages23, out: [loadStage2: TRUE ] ];
Set[ s: loadStages23, out: [loadStage3: TRUE ] ];
Set[ s: BETrue[[x2ASrcLit1: TRUE]], out: [x2ASrcLit2: TRUE ] ]};
GenPhAOutputs:
PROC = {
cur, temp: PO.BoolExpr;
notCondEffect1Bubble:
PO.BoolExpr ←
PO.Not[BE[m: [condEffect1: condEffectIsSig], d: [condEffect1: bubble]]];
stage1BHolding:
PO.BoolExpr ←
PO.Or[
BETrue[[reset: TRUE]],
PO.And[
notCondEffect1Bubble,
PO.Or[ BETrue[[stage1BHold: TRUE]], BETrue[[dPReject: TRUE]] ] ] ];
eUStkOverflow:
PO.BoolExpr ←
PO.And[
BETrue[[trapsEnbled2: TRUE]],
BETrue[[eStkOverflow2: TRUE]]
];
ifuStkOverflow:
PO.BoolExpr ←
PO.And[
BETrue[[trapsEnbled2: TRUE]],
BETrue[[iStkNearlyFull: TRUE]],
PO.Or[
BETrue[[dPFaulted: TRUE]],
PO.And[
BEFalse[[dPReject: TRUE]],
PO.Or[
BETrue[[push2: TRUE]],
BETrue[[eStkOverflow2: TRUE]],
BETrue[[instFault2: TRUE]],
PO.And[BETrue[[instStarting2: TRUE]], BETrue[[rschWaiting2: TRUE]]],
PO.And[
BETrue[[eUCondition2: TRUE]],
BE[ m: [condEffect2: condEffectIsSig], d: [condEffect2: macroTrap] ]
]
]
]
]
];
interlock:
PO.BoolExpr ←
PO.And[
PO.Or[
BETrue[[stage1BHold: TRUE]],
PO.And[
BETrue[[stage1HoldIfReject: TRUE]],
BETrue[[dPReject: TRUE]]
]
],
notCondEffect1Bubble
];
Set[ s: BETrue[[dPFaulted: TRUE]], out:[ stage3BCPipe: abort ] ];
Set[ s: stage1BHolding, out:[
stage1BHolding: TRUE,
notBcLoadStage1: TRUE ] ];
Reset
Set[s: BETrue[[reset:
TRUE]], out:[
stage2B: abort,
microExcptJmp: resetting,
except: [specialCode, reset] ] ];
cur ← BEFalse[[reset: TRUE]];
Intermediate cycle of protected microinstruction sequence
Set[s:
PO.And[cur, BETrue[[protMicroCycle:
TRUE]]], out:[
microExcptJmp: none,
except: [specialCode, none] ] ];
cur ← PO.And[cur, BEFalse[[protMicroCycle: TRUE]]];
IFU stack overflow
Set[s:
PO.And[cur, ifuStkOverflow], out:[
stage2B: abort,
microExcptJmp: trap,
except: [specialCode, iStkOFlow] ] ];
cur ← PO.And[cur, PO.Not[ifuStkOverflow]];
Data PBus Fault, pipe stage 3
Set[s:
PO.And[cur, BETrue[[dPFaulted:
TRUE]]], out:[
stage2B: abort,
microExcptJmp: trap,
except: [dpFault] ] ];
cur ←
PO.And[cur, BEFalse[[dPFaulted:
TRUE]]];
Reject
Set[s: PO.And[cur, BETrue[[dPReject: TRUE]], interlock], out: forceBubble ];
cur ← PO.And[cur, BEFalse[[dPReject: TRUE]]];
ALU Condition, pipe stage 2
temp ← PO.And[cur, BETrue[[eUCondition2: TRUE]]];
Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: macroTrap], out:[
stage2B: abort,
microExcptJmp: trap,
except: [condCode] ] ];
Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: macroJump], out:[
stage2B: abort,
microExcptJmp: cJump,
except: [specialCode, cJump] ] ];
Set[s:temp, m:[condEffect2: condEffectIsSig], d:[condEffect2: microJump], out:[
microExcptJmp: microJump ] ];
cur ← PO.And[cur, BEFalse[[eUCondition2: TRUE]]];
EU stack overflow, pipe stage 2
Set[s:
PO.And[cur, eUStkOverflow], out:[
stage2B: abort,
microExcptJmp: trap,
except: [specialCode, eStkOFlow] ] ];
cur ← PO.And[cur, PO.Not[eUStkOverflow]];
Pipe Interlock
Set[s: PO.And[cur, interlock], out: forceBubble ];
cur ← PO.And[cur, PO.Not[interlock]];
cur ←
PO.And[cur, BETrue[[instStarting2:
TRUE]] ];
Reschedule Waiting, pipe stage 2
Set[s:
PO.And[cur, BETrue[[trapsEnbled2:
TRUE]], BETrue[[rschWaiting2:
TRUE]]], out:[
stage2B: abort,
microExcptJmp: trap,
except: [specialCode, rschlWait] ]];
cur ← PO.And[cur, PO.Or[BEFalse[[rschWaiting2: TRUE]], BEFalse[[trapsEnbled2: TRUE]]]];
Instruction Fetch Fault, pipe stage 2
Set[s:cur, m:[instFault2:
TRUE], d:[instFault2:
TRUE], out:[
stage2B: abort,
microExcptJmp: trap,
except: [specialCode, ipFault] ]];
cur ← PO.And[cur, BEFalse[[instFault2: TRUE]]];
ELSE new unexceptional microinstruction [ ]
};