<> <> <> <> IFUPLAMainPipeControl: CEDAR DEFINITIONS = BEGIN MainPipeControlIn: TYPE = RECORD [ -- default must be zero <> reset: BOOL _ FALSE, dPReject: BOOL _ FALSE, dPFaulting: BOOL _ FALSE, protMicroCycle: BOOL _ FALSE, microExcptJmpBubble: BOOL _ FALSE, -- feedback stage2BAbort: BOOL _ FALSE, -- feedback stage1BHold: BOOL _ FALSE, condEffect1: CondEffect _ VAL[0], -- for detecting bubble in 1B condEffect2: CondEffect _ VAL[0], eUCondition2: BOOL _ FALSE, trapsEnabled2: BOOL _ FALSE, eStkOverflow2: BOOL _ FALSE, instStarting2: BOOL _ FALSE, reschedule: BOOL _ FALSE, rschWaiting: BOOL _ FALSE, push2: BOOL _ FALSE, instFault2: BOOL _ FALSE, iStkNearlyFull: BOOL _ FALSE, <> rschClear: BOOL _ FALSE ]; -- from output MainPipeControlOut: TYPE = RECORD [ <> stage2A: NormalBubble _ normal, stage3A: NormalAbort _ normal, loadStage1: BOOL _ FALSE, loadStage2: BOOL _ FALSE, loadStage3: BOOL _ FALSE, <> stage1BHolding: BOOL _ FALSE, notBcLoadStage1: BOOL _ FALSE, -- really just stage1BHolding again stage2B: NormalAbort _ normal, -- to input next phase (abort) stage3BCPipe: NormalAbort _ normal, microExcptJmp: MicroExcptJmp _ none, -- to input next phase (bubble) except: Exception _ [specialCode, none], rschClear: BOOL _ FALSE, -- to input same phase rschWaiting: BOOL _ FALSE ]; -- to input next phase NormalBubble: TYPE = MACHINE DEPENDENT {normal(0), bubble(1)}; NormalAbort: TYPE = MACHINE DEPENDENT {normal(0), abort(1)}; CondEffect: TYPE = MACHINE DEPENDENT {macroTrap(0), macroJump, microJump, bubble(3)}; fixedMicroJump: [0..256) = 48; MicroExcptJmp: TYPE = MACHINE DEPENDENT { none(0), -- microcycle = CurrentCycle MOD 128 bubble(3), -- microcycle = CurrentCycle MOD 128 + 128 microJump(5), -- microcycle = 48 = fixedMicroJump resetting(9), -- microcycle = 112 trap(17), -- microcycle = 116 cJump(33)}; -- microcycle = 120 Exception: TYPE = RECORD [type: ExceptType, code: ExceptCode _ none]; -- for Trap PC generator ExceptType: TYPE = MACHINE DEPENDENT {specialCode(0), condCode(3), dpFault(5)}; ExceptCode: TYPE = MACHINE DEPENDENT { none (0), ipFault (1), bubble (2), cJump (3), reseting (6), reset (7), iStkOFlow (8), eStkOFlow (9), rschlWait (0AH), trapCycle1 (0BH)}; <<>> <> <> < no other bit is true).>> <> <<>> END.