<> <> <> <> <<>> DIRECTORY Commander, Dragon, DragOpsCross, IFUPLAInterlock, IO, PLAOps; IFUPLAInterlockImpl: CEDAR PROGRAM IMPORTS Commander, IO, PLAOps = BEGIN OPEN IFUPLAInterlock, PLAOps; InterlockPLA: PLAOps.PLA; <> GenInterlockPLA: PROC = { read2: BoolExpr _ BE[m:[dPCmndIsRd2: TRUE], d:[dPCmndIsRd2: TRUE]]; <> ac2: BoolExpr _ BE[m:[a1IsC2: TRUE], d:[a1IsC2: TRUE]]; bc2: BoolExpr _ BE[m:[b1IsC2: TRUE], d:[b1IsC2: TRUE]]; ac3: BoolExpr _ BE[m:[a1IsC3: TRUE], d:[a1IsC3: TRUE]]; bc3: BoolExpr _ BE[m:[b1IsC3: TRUE], d:[b1IsC3: TRUE]]; kIsRtOp: BoolExpr _ BE[m:[kIsRtOp1: TRUE], d:[kIsRtOp1: TRUE]]; fCtlIsRtOp: BoolExpr _ BE[m:[fCtlIsRtOp1: TRUE], d:[fCtlIsRtOp1: TRUE]]; cField2: BoolExpr _ BE[m:[cIsField2: TRUE], d:[cIsField2: TRUE]]; cField3: BoolExpr _ BE[m:[cIsField3: TRUE], d:[cIsField3: TRUE]]; <> <> aluRtFromB: BoolExpr _ Not[ Or[ kIsRtOp, fCtlIsRtOp ]]; interlock2: BoolExpr _ And[ read2, Or[ ac2, bc2, And[ fCtlIsRtOp, cField2 ]]]; <> <> <> <<];>> <<>> <> <<= stage1BHold OR (DPReject AND stage1BHoldIfReject)>> Set[s: interlock2, out: [stage1BHold: TRUE ] ]; <> <<>> <> <> Set[s: ac2, out:[eUAluLeftSrc1: rBus]]; Set[s: And[Not[ ac2], ac3], out:[eUAluLeftSrc1: cBus]]; Set[s: And[Not[ ac2], Not[ ac3]], out:[eUAluLeftSrc1: aBus]]; <<>> <> Set[s: kIsRtOp, out:[eUAluRightSrc1: kBus]]; Set[s: And[ fCtlIsRtOp, cField2 -- , Not[read2] -- ], out:[eUAluRightSrc1: rBus]]; Set[s: And[ fCtlIsRtOp, Or[Not[cField2] -- , read2 -- ], cField3], out:[eUAluRightSrc1: cBus]]; Set[s: And[ fCtlIsRtOp, Or[Not[cField2] -- , read2 -- ], Not[cField3]], out:[eUAluRightSrc1: fCtlReg]]; Set[s: And[ aluRtFromB, bc2 -- , Not[read2] -- ], out:[eUAluRightSrc1: rBus]]; Set[s: And[ aluRtFromB, Or[Not[bc2] -- , read2 -- ], bc3], out:[eUAluRightSrc1: cBus]]; Set[s: And[ aluRtFromB, Or[Not[bc2] -- , read2 -- ], Not[bc3]], out:[eUAluRightSrc1: bBus]]; <<>> <> Set[s: And[ bc2 -- , Not[read2] -- ], out:[eUStore2ASrc1: rBus]]; Set[s: And[ Or[Not[bc2] -- , read2 -- ], bc3], out:[eUStore2ASrc1: cBus]]; Set[s: And[ Or[Not[bc2] -- , read2 -- ], Not[bc3]], out:[eUStore2ASrc1: bBus]]; <> Set[s: bc2, out:[eUSt3AIsCBus1: TRUE]]; }; BE: PROC [m, d: InterlockIn] RETURNS[BoolExpr] = { mRef: REF InterlockIn _ NARROW[InterlockPLA.mask]; dRef: REF InterlockIn _ NARROW[InterlockPLA.data]; mRef^ _ m; dRef^ _ d; RETURN[GetBEForDataMask[InterlockPLA]]}; Set: PROC [s: BoolExpr _ NIL, m, d: InterlockIn _ [ ], out: InterlockOut] = { res: REF InterlockOut _ NARROW[InterlockPLA.out]; IF s=NIL THEN s _ BE[m,d] ELSE s _ And[s, BE[m,d] ]; res^ _ out; SetOutForBE[InterlockPLA, s]}; GenInterlock: Commander.CommandProc = { filename: IO.ROPE _ DefaultCMDLine[cmd.commandLine, defaultFile]; InterlockPLA _ NewPLA["IFUPLAInterlock.InterlockIn", "IFUPLAInterlock.InterlockOut"]; GenInterlockPLA[]; [ ] _ ConvertTermListToCompleteSum[InterlockPLA.termList, FALSE, FALSE, cmd.out]; [ ] _ FindAMinimalCover[InterlockPLA.termList, 120, cmd.out]; WritePLAFile[filename, cmd.out, InterlockPLA] }; doc: IO.ROPE = "Expects the name of the ttt file"; defaultFile: IO.ROPE = "IFUPLAInterlock.ttt"; Commander.Register[key:"GenInterlock", proc: GenInterlock, doc: doc]; END. <<>> <<>> <<>>