[Indigo]<Dragon>IFU>IFUPLA>IFUPLAInstrDecodeImpl4.mesa!5

EXPORTS IFUPLAInstrDecode =

BEGIN OPEN IFUPLAInstrDecode, PLAOps;

GenInstrDecodePLA4: PUBLIC GenInstrDecodePLAProc = {

current ← old;

cycle0: BoolExpr ← BE[m:[state: ByteTopSig[8]], d:[state: 0]];

cycle1: BoolExpr ← BE[m:[state: ByteTopSig[8]], d:[state: 1]];

cycle2: BoolExpr ← BE[m:[state: ByteTopSig[8]], d:[state: 2]];

cycle3: BoolExpr ← BE[m:[state: ByteTopSig[8]], d:[state: 3]];

fpEnabled: BoolExpr ← BE[m:[fpEnabled: TRUE], d:[fpEnabled: TRUE]];

GenInstrDecodePLASFP: PROC = {

either: BoolExpr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dSFP]]];

aluInstr: BoolExpr ← And[BE[m:[alpha: 200B], d:[alpha: 000B]], either ];

multInstr: BoolExpr ← And[BE[m:[alpha: 200B], d:[alpha: 200B]], either ];

mode: BoolExpr ← BE[m:[alpha: 100B], d:[alpha: 100B]];

argClr: BoolExpr ← BE[m:[alpha: 003B], d:[alpha: 000B]];

argSgl: BoolExpr ← BE[m:[alpha: 003B], d:[alpha: 001B]];

argDbl: BoolExpr ← BE[m:[alpha: 003B], d:[alpha: 002B]];

argInt: BoolExpr ← BE[m:[alpha: 003B], d:[alpha: 003B]];

Set[s: And[either, Not[fpEnabled]], out: MultiByteXop];

either ← And[either, fpEnabled];

aluInstr ← And[aluInstr, fpEnabled];

multInstr ← And[multInstr, fpEnabled];

Mode

Set[s: And[mode, cycle0, aluInstr], out:[

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next,

bReg: abStackTop,

cReg: ifuFPModeAlu ] ];

Set[s: And[mode, cycle0, multInstr], out: [

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next,

bReg: abStackTop,

cReg: ifuFPModeMult ] ];

Set[s: And[mode, cycle1, either], out: NoOpMicro];

Set[s: And[mode, cycle2, either], out: NoOpMicro];

Set[s: And[mode, cycle3, either], out:[popSa: TRUE ]];

either ← And[either, Not[mode]];

aluInstr ← And[aluInstr, Not[mode]];

multInstr ← And[multInstr, Not[mode]];

Load

Set[s: either, out: [notPassRtIfAZero: TRUE]];

Set[s: And[aluInstr, argClr], out: [cReg: fpAluClr ]];

Set[s: And[multInstr, argClr], out: [cReg: fpMultClr ]];

Set[s: And[aluInstr, argSgl], out: [

aReg: [s, zero], popSa: TRUE,

x2ALitSource: fpLdSglAUnMsw,

cReg: fpAluSgl,

epCmnd: FPLdAlu ] ];

Set[s: And[aluInstr, argDbl, cycle0], out: [

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next,

aReg: [s, offset, zero], popSa: TRUE,

x2ALitSource: fpLdLswAUnLsw,

cReg: fpAluLsw,

epCmnd: FPLdAlu ] ];

Set[s: And[aluInstr, argDbl, cycle1], out: [

aReg: [s, offset, zero], popSa: TRUE,

x2ALitSource: fpLdMswAUnMsw,

cReg: fpAluMsw,

epCmnd: FPLdAlu ] ];

Set[s: And[aluInstr, argInt], out: [

aReg: [s, zero], popSa: TRUE,

x2ALitSource: fpLdMswAUnMsw,

cReg: fpAluMsw,

epCmnd: FPLdAlu ] ];

Set[s: And[multInstr, argSgl], out: [

aReg: [s, offset, zero], popSa: TRUE,

x2ALitSource: fpLdSglAUnMsw,

cReg: fpMultSgl,

epCmnd: FPLdMult ] ];

Set[s: And[multInstr, argDbl, cycle0], out: [

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next,

aReg: [s, offset, zero], popSa: TRUE,

x2ALitSource: fpLdLswAUnLsw,

cReg: fpMultLsw,

epCmnd: FPLdMult ] ];

Set[s: And[multInstr, argDbl, cycle1], out: [

aReg: [s, offset, zero], popSa: TRUE,

x2ALitSource: fpLdMswAUnMsw,

cReg: fpMultMsw,

epCmnd: FPLdMult ] ];

Set[s: And[multInstr, argInt], out: [

aReg: [s, offset, zero], popSa: TRUE,

x2ALitSource: fpLdMswAUnMsw,

cReg: fpMultMsw,

epCmnd: FPLdMult ] ] };

GenInstrDecodePLAFLOP: PROC = {

either: BoolExpr ← And[current,BE[m: [op: InstrTopSig[8]], d:[op: dFLOP]]];

aluInstr: BoolExpr;

multInstr: BoolExpr;

toStack: BoolExpr ← BE[m:[alpha: 100B], d:[alpha: 100B]];

odd: BoolExpr ← BE[m:[alpha: 001B], d:[alpha: 001B]];

argNone: BoolExpr ← BE[m:[beta: ByteTopSig[2]], d:[beta: 000B]];

argSgl: BoolExpr ← BE[m:[beta: ByteTopSig[2]], d:[beta: 100B]];

argDbl: BoolExpr ← BE[m:[beta: ByteTopSig[2]], d:[beta: 200B]];

resNone: BoolExpr ← BE[m:[alpha: 260B], d:[alpha: 040B]]; -- alu compare

resSgl: BoolExpr ← And[Not[resNone], Not[odd]];

resDbl: BoolExpr ← And[Not[resNone], odd];

cycle58: BoolExpr ← BE[m:[state: ByteTopSig[8]], d:[state: 58]];

cycle59: BoolExpr ← BE[m:[state: ByteTopSig[8]], d:[state: 59]];

pcNext: fromPCBus,

microCycleNext: next,

wait: InstrDecodeOut ← [

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next,

notPassRtIfAZero: TRUE];

Set[s: And[either, Not[fpEnabled]], out: MultiByteXop];

either ← And[either, fpEnabled];

aluInstr ← And[either, BE[m:[alpha: ByteTopSig[1]], d:[alpha: 000B]]];

multInstr ← And[either, BE[m:[alpha: ByteTopSig[1]], d:[alpha: 200B]]];

Cycles 0..3

Set[s: either, out: [notPassRtIfAZero: TRUE]];

Set[s: And[either, Or[cycle0, cycle1, cycle2, cycle3] ], out: [

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next ]];

Set[s: And[either, cycle0], out: [aReg: [s, zero]]];

Set[s: And[either, cycle1, argDbl], out: [aReg: [s, minus1]]];

Set[s: And[either, cycle0, argSgl], out: [x2ALitSource: fpLdSglBSt]];

Set[s: And[aluInstr, cycle0, argDbl], out: [x2ALitSource: fpLdLswB]];

Set[s: And[multInstr, cycle0, argDbl], out: [x2ALitSource: fpLdLswBSt]];

Set[s: And[aluInstr, cycle1, argDbl], out: [x2ALitSource: fpLdMswBSt]];

Set[s: And[multInstr, cycle1, argDbl], out: [x2ALitSource: fpLdMswB]];

Set[s: And[aluInstr, cycle0], out: [epCmnd: FPLdAlu]];

Set[s: And[multInstr, cycle0], out: [epCmnd: FPLdMult]];

Set[s: And[aluInstr, cycle1, argDbl], out: [epCmnd: FPLdAlu]];

Set[s: And[multInstr, cycle1, argDbl], out: [epCmnd: FPLdMult]];

Set[s: And[either, cycle0, Or[argNone, argSgl] ], out: [microJump: TRUE]];

Set[s: And[either, cycle1, argDbl], out: [microJump: TRUE]];

Cycles 4..57

Set[s: either, m:[state: ByteTopSig[6]], d:[state: 4], out: wait]; -- 4.. 7

Set[s: either, m:[state: ByteTopSig[5]], d:[state: 8], out: wait]; -- 8..15

Set[s: either, m:[state: ByteTopSig[4]], d:[state: 16], out: wait]; -- 16..31

Set[s: either, m:[state: ByteTopSig[4]], d:[state: 32], out: wait]; -- 32..47

Set[s: either, m:[state: ByteTopSig[5]], d:[state: 48], out: wait]; -- 48..55

Set[s: either, m:[state: ByteTopSig[7]], d:[state: 56], out: wait]; -- 56..57

Cycles 58..59

Set[s: And[either, cycle58], out: [fpCheckStatus: TRUE]];

Set[s: And[either, resDbl, cycle58], out: [

nextMacro: hold,

pcNext: fromPCBus,

microCycleNext: next ]];

Set[s: And[aluInstr, Or[

And[cycle58, resNone],

And[cycle58, resSgl, toStack],

And[cycle58, resDbl, toStack],

And[cycle59, resDbl, toStack] ] ], out: [epCmnd: FPUnAlu] ];

Set[s: And[multInstr, Or[

And[cycle58, resNone],

And[cycle58, resSgl, toStack],

And[cycle58, resDbl, toStack],

And[cycle59, resDbl, toStack] ] ], out: [epCmnd: FPUnMult] ];

Set[s: And[aluInstr, Or[

And[cycle58, resSgl, Not[toStack]],

And[cycle58, resDbl, Not[toStack]],

And[cycle59, resDbl, Not[toStack]] ] ], out: [epCmnd: FPXfrAlu] ];

Set[s: And[multInstr, Or[

And[cycle58, resSgl, Not[toStack]],

And[cycle58, resDbl, Not[toStack]],

And[cycle59, resDbl, Not[toStack]] ] ], out: [epCmnd: FPXfrMult]];

Set[s: And[either, cycle58, resSgl], out: [x2ALitSource: fpLdSglAUnMsw]];

Set[s: And[either, cycle58, resDbl], out: [x2ALitSource: fpLdMswAUnMsw]];

Set[s: And[either, cycle59, resDbl], out: [x2ALitSource: fpLdLswAUnLsw]];

Set[s: And[cycle58, resSgl, aluInstr, Not[toStack]], out: [cReg: fpAluSgl ]];

Set[s: And[cycle58, resSgl, multInstr, Not[toStack]], out: [cReg: fpMultSgl ]];

Set[s: And[cycle58, resDbl, aluInstr, Not[toStack]], out: [cReg: fpAluMsw ]];

Set[s: And[cycle58, resDbl, multInstr, Not[toStack]], out: [cReg: fpMultMsw ]];

Set[s: And[cycle59, resDbl, aluInstr, Not[toStack]], out: [cReg: fpAluLsw ]];

Set[s: And[cycle59, resDbl, multInstr, Not[toStack]], out: [cReg: fpMultLsw ]];

either ← And[either, toStack];

Set[s: And[either, cycle58, resNone, argSgl], out: [ popSa: TRUE]];

Set[s: And[either, cycle58, resNone, argDbl], out: [ popSb: TRUE, popSa: TRUE]];

Set[s: And[either, cycle58, resSgl, argNone], out: [cReg: [s, offset, one], pushSc: TRUE]];

Set[s: And[either, cycle58, resSgl, argSgl], out: [cReg: [s, offset, zero] ]];

Set[s: And[either, cycle58, resSgl, argDbl], out: [cReg: [s, offset, minus1], popSa: TRUE]];

Set[s: And[either, cycle58, resDbl, argNone], out: [cReg:[s,offset,offset,one],pushSc:TRUE]];

Set[s: And[either, cycle58, resDbl, argSgl], out: [cReg: [s, offset, zero],pushSc: TRUE]];

Set[s: And[either, cycle58, resDbl, argDbl], out: [cReg: [s, offset,minus1]]];

Set[s: And[either, cycle59, resDbl, argNone], out: [cReg: [s, offset, two],pushSc: TRUE]];

Set[s: And[either, cycle59, resDbl, argSgl], out: [cReg: [s, offset, one]]];

Set[s: And[either, cycle59, resDbl, argDbl], out: [cReg: [s, offset, zero]]]};

GenInstrDecodePLASFP[];

GenInstrDecodePLAFLOP[];

};

END.