<> <> <> <> <> <> <<>> DIRECTORY DragOpsCross, IFUPLAInstrDecode, PLAOps; IFUPLAInstrDecodeImpl2: CEDAR PROGRAM IMPORTS IFUPLAInstrDecode, PLAOps EXPORTS IFUPLAInstrDecode = BEGIN OPEN IFUPLAInstrDecode, PLAOps; GenInstrDecodePLA2: PUBLIC GenInstrDecodePLAProc = { instr: BoolExpr; userMode0: BoolExpr _ BE[m:[userMode0: TRUE], d:[userMode0: TRUE]]; current _ old; <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<>> Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRB], out:[ aReg: abStackTop, x2ALitSource: alpha, cReg: cStackTop, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRSB], out:[ aReg: abStackTop, x2ALitSource: alpha, cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLRI0], out:[ aReg: [ l, op47 ], x2ALitSource: alpha, cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; <<>> Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLGF], out:[ -- Save me for lisp aReg: euGF, x2ALitSource: alphaBeta, cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRRI], out:[ aReg: [ l, beta47], x2ALitSource: alpha, cReg: [ l, beta03 ], aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRAI], out:[ aReg: [ aBase, beta47], x2ALitSource: alpha, cReg: [ l, beta03 ], aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dCST]]]; Set[s: And[instr, userMode0], m:[state: ByteTopSig[8]], d:[state: 0], out:[condSel: AddressCheckFault]]; Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[ nextMacro: hold, pcNext: fromPCBus, microCycleNext: next, aReg: [ s, offset, minus2 ], x2ALitSource: alpha, cReg: [ s, offset, one ], aluOp: VAdd, dPCmnd: FetchHold, dPCmndIsRd0: TRUE ]]; <> Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[ nextMacro: hold, pcNext: fromPCBus, microCycleNext: next, aReg: [ s, offset, one ], bReg: abStackTop, aluOp: VSub, condSel: EZ, condEffect0: microJump ]]; -- IF [S+1] = [S] THEN microJump Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 2], out:NoOpMicro]; -- wait Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 3], out:NoOpMicro]; -- wait Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 4], out:[ -- [] _ ([S-2]+alpha)^, hold off, S_S+1 aReg: [ s, offset, minus2 ], x2ALitSource: alpha, pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; <> <<([S-2]+alpha)^ _ [S-1], release hold, S _ S+1>> <<>> <> <<>> Set[s:And[BE[m: [instReady: TRUE], d: [instReady: TRUE]], BE[m: [op: InstrTopSig[8]], d: [op: dCST]]], m:[state: ByteTopSig[8]], d:[state: fixedMicroJump], out:[ aReg: [ s, offset, minus2 ], bReg: [ s, offset, minus1 ], x2ALitSource: alpha, pushSc: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWB]], userMode0], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWB]]], out: [ aReg: abStackTop, bReg: [ s, offset, minus1 ], x2ALitSource: alpha, popSa: TRUE, popSb: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWSB]],userMode0], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWSB]]], out: [ aReg: [ s, offset, minus1 ], bReg: abStackTop, x2ALitSource: alpha, popSa: TRUE, popSb: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dPSB]],userMode0], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPSB]]], out: [ aReg: [ s, offset, minus1 ], bReg: abStackTop, x2ALitSource: alpha, popSa: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s:And[current,BE[m:[op: InstrTopSig[4]], d:[op: dSRI0]],userMode0], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[4]], d:[op: dSRI0]]], out: [ aReg: [ l, op47 ], bReg: abStackTop, x2ALitSource: alpha, popSb: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWRI]],userMode0], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWRI]]], out: [ aReg: [ l, beta47], bReg: [ l, beta03 ], x2ALitSource: alpha, aluOp: VAdd, dPCmnd: Store ]]; Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWAI]],userMode0], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWAI]]], out: [ aReg: [ aBase, beta47], bReg: [ l, beta03 ], x2ALitSource: alpha, aluOp: VAdd, dPCmnd: Store ]]; <> Set[s: And[ current, BE[m:[op: InstrTopSig[6]], d:[op: dIOS]], userMode0, BE[m:[beta: 4], d:[beta: 4]] -- kernel mode required ], out: [condSel: ModeFault -- always traps -- ]]; Set[s: And[ current, BE[m:[op: InstrTopSig[6]], d:[op: dIOS]] ], out: [dPCmndSel: beta]]; -- feed beta to PBus command Set[s: And[ current, BE[m:[op: InstrTopSig[6]], d:[op: dIOS]], BE[m:[beta: 1], d:[beta: 0]] ], out: [dPCmndIsRd0: TRUE]]; Set[s: And[ current, BE[m:[op: InstrTopSig[6]], d:[op: dIOS]], userMode0, BE[m:[beta: 6], d:[beta: 2]] -- operation needs address protection ], out: [condSel: AddressCheckFault]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIOS]], BE[m:[beta:1], d:[beta:0]]], out: [ aReg: abStackTop, <> cReg: cStackTop, <> x2ALitSource: alpha, aluOp: VAdd ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIOS]], BE[m:[beta:1], d:[beta:1]]], out: [ aReg: abStackTop, popSa: TRUE, bReg: [s, offset, minus1], popSb: TRUE, x2ALitSource: alpha, aluOp: VAdd ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIOL]], BE[m:[beta:1], d:[beta:0]]], out: [ aReg: constantZero, cReg: [s, offset, one], pushSc: TRUE, x2ALitSource: alpha, aluOp: Or ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIOL]], BE[m:[beta:1], d:[beta:1]]], out: [ aReg: constantZero, bReg: abStackTop, popSb: TRUE, x2ALitSource: alpha, aluOp: Or ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dION]], BE[m:[beta:1], d:[beta:0]]], out: [ aReg: constantZero, cReg: [s, offset, one], <> x2ALitSource: alpha, aluOp: Or ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dION]], BE[m:[beta:1], d:[beta:1]]], out: [ aReg: constantZero, bReg: abStackTop, x2ALitSource: alpha, aluOp: Or ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dFSDB], out:[ aluOp: VAdd, aReg: [s, offset, zero], x2ALitSource: alphaBeta, cReg: euField, cIsField0: TRUE, popSa: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIB], out:[ x2ALitSource: alpha, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIDB], out:[ x2ALitSource: alphaBeta, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIQB], out:[ x2ALitSource: alpBetGamDel, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[5]], d:[op: dLC0], out:[ bReg: [ cBase, op47 ], cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLR0], out:[ bReg: [ l, op47 ], cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[4]], d:[op: dSR0], out:[ bReg: [ s, offset, zero ], cReg: [ l, op47 ], popSb: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dDUP], out:[ bReg: abStackTop, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dEXDIS], out:[ bReg: abStackTop, cReg: [ s, offset, minus1 ], popSa: TRUE ]]; }; END.