IFUPLAInstrDecode2.mesa
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Curry, September 10, 1985 2:52:08 pm PDT
Herrmann, August 14, 1985 12:59:44 pm PDT
McCreight, October 18, 1985 12:24:37 pm PDT
DIRECTORY
DragOpsCross,
IFUPLA,
PLAOps;
IFUPLAInstrDecode2: CEDAR PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PLAOps;
GenInstrDecodePLA2: PUBLIC GenInstrDecodePLAProc = {
instr:   BoolExpr;
userMode: BoolExpr ← BE[m:[userMode:  TRUE], d:[userMode:  TRUE]];
current ← old;
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIN]], userMode], out: MultiByteXop];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIN]], Not[userMode]], out: [
aReg: abStackTop,
xaSource: alpha,
cReg: cStackTop,
aluOp: VAdd,
dpCmnd: IOFetch,
dmCmndIsRd: TRUE ]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPIN]], userMode], out: MultiByteXop];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPIN]], Not[userMode]], out: [
aReg: abStackTop,
xaSource: alpha,
cReg: cStackTop,
aluOp: VAdd,
dpCmndSel: beta,
dpCmndIsRd: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRB], out:[
aReg: abStackTop,
xaSource: alpha,
cReg: cStackTop,
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRSB], out:[
aReg: abStackTop,
xaSource: alpha,
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE
]];
Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLRI0], out:[
aReg: [ l, op47 ],
xaSource: alpha,
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLGF], out:[ -- Save me for lisp
aReg: euGF,
xaSource: alphaBeta,
cReg: [ s, offset, one ],
pushSc: TRUE,
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRRI], out:[
aReg: [ l, beta47],
xaSource: alpha,
cReg: [ l, beta03 ],
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRAI], out:[
aReg: [ aBase, beta47],
xaSource: alpha,
cReg: [ l, beta03 ],
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE ]];
instr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dCST]]];
Set[s: And[instr, userMode], m:[state: ByteTopSig[8]], d:[state: 0], out:[condSel: Kernal]];
Set[s: instr,     m:[state: ByteTopSig[8]], d:[state: 0], out:[
nextMacro: dontGet,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, minus2 ],
xaSource: alpha,
cReg: [ s, offset, one ],
aluOp: VAdd,
dpCmnd: FetchHold,
dpCmndIsRd: TRUE ]];
This cycle will invariably be Delayed (automatically) by the pipe since cycle 0 was a fetch into S+1
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[
nextMacro: dontGet,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, one ],
bReg: abStackTop,
aluOp: VSub,
condSel: EZ,
condEffect: microJump ]]; -- IF [S+1] = [S] THEN microJump
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 2], out:NoOpMicro]; -- wait
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 3], out:NoOpMicro]; -- wait
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 4], out:[ -- [] ← ([S-2]+alpha)^, hold off, S←S+1
aReg: [ s, offset, minus2 ],
xaSource: alpha,
pushSc: TRUE,
aluOp: VAdd,
dpCmnd: Fetch,
dpCmndIsRd: TRUE ]];
Remember that when doing microjumps, you can't get next macro until the condition has been tested since the opcode must be the same (cycles 2 and 3 above are necessary).
([S-2]+alpha)^ ← [S-1], release hold, S ← S+1
Set[s:instr, m:[state: ByteTopSig[8]], d:[state: fixedMicroJump], out:[
aReg: [ s, offset, minus2 ],
bReg: [ s, offset, minus1 ],
xaSource: alpha,
pushSc: TRUE,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dOUT]], userMode], out: MultiByteXop];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dOUT]], Not[userMode]], out: [
aReg: abStackTop,
bReg: [ s, offset, minus1 ],
xaSource: alpha,
popSa: TRUE,
popSb: TRUE,
aluOp: VAdd,
dpCmnd: IOStore ]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPOUT]], userMode], out: MultiByteXop];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPOUT]], Not[userMode]], out: [
aReg: abStackTop,
bReg: [ s, offset, minus1 ],
xaSource: alpha,
popSa: TRUE,
popSb: TRUE,
aluOp: VAdd,
dpCmndSel: beta ]];
Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWB]], userMode], out: [condSel: Kernal]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWB]]], out: [
aReg: abStackTop,
bReg: [ s, offset, minus1 ],
xaSource: alpha,
popSa: TRUE,
popSb: TRUE,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWSB]],userMode], out: [condSel: Kernal]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWSB]]], out: [
aReg: [ s, offset, minus1 ],
bReg: abStackTop,
xaSource: alpha,
popSa: TRUE,
popSb: TRUE,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dPSB]],userMode], out: [condSel: Kernal]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPSB]]], out: [
aReg: [ s, offset, minus1 ],
bReg: abStackTop,
xaSource: alpha,
popSa: TRUE,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dSRI0]],userMode], out: [condSel: Kernal]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dSRI0]]], out: [
aReg: [ l, op47 ],
bReg: abStackTop,
xaSource: alpha,
popSb: TRUE,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWRI]],userMode], out: [condSel: Kernal]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWRI]]], out: [
aReg: [ l, beta47],
bReg: [ l, beta03 ],
xaSource: alpha,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s:And[current,BE[m:[op: InstrTopSig[8]], d:[op: dWAI]],userMode], out: [condSel: Kernal]];
Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWAI]]], out: [
aReg: [ aBase, beta47],
bReg: [ l, beta03 ],
xaSource: alpha,
aluOp: VAdd,
dpCmnd: Store ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dFSDB], out:[
aluOp: VAdd,
aReg: [s, offset, zero],
xaSource: alphaBeta,
cReg: euField,
popSa: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIB], out:[
xaSource: alpha,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIDB], out:[
xaSource: alphaBeta,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIQB], out:[
xaSource: alpBetGamDel,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[5]], d:[op: dLC0], out:[
bReg: [ cBase, op47 ],
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLR0], out:[
bReg: [ l, op47 ],
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[4]], d:[op: dSR0], out:[
bReg: [ s, offset, zero ],
cReg: [ l, op47 ],
popSb: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dDUP], out:[
bReg: abStackTop,
cReg: [ s, offset, one ],
pushSc: TRUE ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dEXDIS], out:[
bReg: abStackTop,
cReg: [ s, offset, minus1 ],
popSa: TRUE ]];
};
END.