IFUPLAImplB3.mesa
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Curry, November 4, 1984 1:31:45 pm PST
DIRECTORY
DragOpsCross,
IFUPLA,
PLAOps;
IFUPLAImplB3: CEDAR PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;
GeneratePhBPLA3: PUBLIC PROC = {
sglBiAlu:  PO.BoolExpr ←    BE[m:[alpha:351B], d:[alpha:100B]];
sglUnAlu: PO.BoolExpr ← PO.Or[ BE[m:[alpha:351B], d:[alpha:110B]],
           BE[m:[alpha:371B], d:[alpha:160B]],
           BE[m:[alpha:375B], d:[alpha:170B]]];
dblUnAlu: PO.BoolExpr ← PO.Or[ BE[m:[alpha:351B], d:[alpha:111B]],
           BE[m:[alpha:371B], d:[alpha:161B]]];
dblBiAlu:  PO.BoolExpr ←    BE[m:[alpha:351B], d:[alpha:101B]];
sglBiCom:  PO.BoolExpr ←    BE[m:[alpha:371B], d:[alpha:140B]];
dblBiCom: PO.BoolExpr ←    BE[m:[alpha:371B], d:[alpha:141B]];
sglUnCom: PO.BoolExpr ←    BE[m:[alpha:371B], d:[alpha:150B]];
dblUnCom: PO.BoolExpr ←    BE[m:[alpha:371B], d:[alpha:151B]];
sglUnCvt: PO.BoolExpr ← PO.Or[ BE[m:[alpha:373B], d:[alpha:173B]],
           BE[m:[alpha:375B], d:[alpha:174B]]];
dblUnCvt: PO.BoolExpr ←    BE[m:[alpha:373B], d:[alpha:171B]];
sglBiMult: PO.BoolExpr ←    BE[m:[alpha:301B], d:[alpha:200B]];
dblBiMult: PO.BoolExpr ←    BE[m:[alpha:301B], d:[alpha:201B]];
setMode:  PO.BoolExpr ←    BE[m:[alpha:300B], d:[alpha:300B]];
instr:   PO.BoolExpr;
state:   PO.BoolExpr;
m:    MicroInst;
GeneratePhBPLA3a: PROC = {
instrPO.And[current, BE[m:[op: instrIsSig], d:[op: dFP]]];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 0]]];
m ← [
dontGetNextMacro: TRUE,
xBSource:    pc,
euPBusCmd:   StoreFP]; 
m.kASource ← fpLdMode;  Set[s: PO.And[setMode,  state], out:m];
m.bReg  ← [s, zero];
m.kASource ← fpLdAMsw;  Set[s: PO.And[sglUnCom, state], out:m];
m.kASource ← fpLdAMsw;  Set[s: PO.And[sglUnAlu, state], out:m];
m.kASource ← fpLdAMsw;  Set[s: PO.And[sglUnCvt, state], out:m];
m.kASource ← fpLdALsw;  Set[s: PO.And[dblUnCom, state], out:m];
m.kASource ← fpLdALsw;  Set[s: PO.And[dblUnAlu, state], out:m];
m.kASource ← fpLdALsw;  Set[s: PO.And[dblUnCvt, state], out:m];
m.kASource ← fpLdBMsw;  Set[s: PO.And[sglBiCom, state], out:m];
m.kASource ← fpLdBMsw;  Set[s: PO.And[sglBiAlu,  state], out:m];
m.kASource ← fpLdBMsw;  Set[s: PO.And[sglBiMult, state], out:m];
m.kASource ← fpLdBLsw;  Set[s: PO.And[dblBiCom, state], out:m];
m.kASource ← fpLdBLsw;  Set[s: PO.And[dblBiAlu, state], out:m];
m.kASource ← fpLdBLsw;  Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 1]]];
m ← [dontGetNextMacro: FALSE]; Set[s: PO.And[setMode,  state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnCvt, state], out:m];
m ← [
dontGetNextMacro: TRUE,
xBSource: pc,
bReg: [s, minus1],
euPBusCmd: StoreFP];
m.kASource ← fpLdAMsw;   Set[s: PO.And[dblUnCom, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[dblUnAlu, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[dblUnCvt, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[sglBiCom, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[sglBiAlu, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[sglBiMult, state], out:m];
m.kASource ← fpLdBMsw;   Set[s: PO.And[dblBiCom, state], out:m];
m.kASource ← fpLdBMsw;   Set[s: PO.And[dblBiAlu, state], out:m];
m.kASource ← fpLdBMsw;   Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 2]]];
m ← NoOpMicro;     Set[s: PO.And[sglUnCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnCvt, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnCvt, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiMult, state], out:m];
m ← [
dontGetNextMacro: TRUE,
xBSource:   pc,
bReg:    [ s, minus2 ],
euPBusCmd:  StoreFP ];
m.kASource ← fpLdALsw;    Set[s: PO.And[dblBiCom, state], out:m];
m.kASource ← fpLdALsw;    Set[s: PO.And[dblBiAlu, state], out:m];
m.kASource ← fpLdALsw;    Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 3]]];
m ← NoOpMicro;     Set[s: PO.And[sglUnCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglUnCvt, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnCvt, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiMult, state], out:m];
m ← [
dontGetNextMacro: TRUE,
xBSource:   pc,
bReg:    [ s, minus3 ],
euPBusCmd:  StoreFP ];
m.kASource ← fpLdAMsw;   Set[s: PO.And[dblBiCom, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[dblBiAlu, state], out:m];
m.kASource ← fpLdAMsw;   Set[s: PO.And[dblBiMult, state], out:m] };
GeneratePhBPLA3b: PROC = {
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 4]]];
Set[s: PO.And[sglUnCom, state], out:[
dontGetNextMacro: FALSE,
deltaSa:   pop,
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
Set[s: PO.And[sglUnAlu, state], out:[
dontGetNextMacro: FALSE,
cReg:    [ s, zero ],
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
Set[s: PO.And[sglUnCvt, state], out:[
dontGetNextMacro: TRUE,
xBSource:   pc,
cReg:    [ s, zero ],
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
m ← NoOpMicro;     Set[s: PO.And[dblUnCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblUnCvt, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[sglBiMult, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 5]]];
Set[s: PO.And[sglUnCvt, state], out:[
dontGetNextMacro: FALSE,
deltaSc:   push,
cReg:    [ s, one ],
kASource:  fpUnldLsw,
euPBusCmd:  FetchFPAlu ]];
m ← [
dontGetNextMacro: FALSE,
deltaSa:   pop,
deltaSb:   pop,
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ];
Set[s: PO.And[dblUnCom, state], out:m];
Set[s: PO.And[sglBiCom, state], out:m];
Set[s: PO.And[dblUnAlu, state], out:[
dontGetNextMacro: TRUE,
xBSource:   pc,
cReg:    [ s, minus1 ],
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
m ← [
dontGetNextMacro: FALSE,
deltaSa:   pop,
cReg:    [ s, minus1 ],
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ];
Set[s: PO.And[dblUnCvt, state], out:m];
Set[s: PO.And[sglBiAlu, state], out:m];
Set[s: PO.And[sglBiMult, state], out:[
dontGetNextMacro: FALSE,
deltaSa:   pop,
cReg:    [ s, minus1 ],
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPMult ]];
m ← NoOpMicro;     Set[s: PO.And[dblBiCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 6]]];
Set[s: PO.And[dblUnAlu, state], out:[
dontGetNextMacro: FALSE,
cReg:    [ s, zero ],
kASource:  fpUnldLsw,
euPBusCmd:  FetchFPAlu ]];
m ← NoOpMicro;     Set[s: PO.And[dblBiCom, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiAlu, state], out:m];
m ← NoOpMicro;     Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 7]]];
Set[s: PO.And[dblBiCom, state], out:[
dontGetNextMacro: TRUE,
xBSource:   pc,
deltaSa:   pop,
deltaSb:   pop, -- Two more left for next cycle
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
Set[s: PO.And[dblBiAlu, state], out:[
dontGetNextMacro: TRUE,
xBSource:   pc,
cReg:    [ s, minus3 ],
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
m ← NoOpMicro;     Set[s: PO.And[dblBiMult, state], out:m];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 8]]];
Set[s: PO.And[dblBiCom, state], out:[
dontGetNextMacro: FALSE,
deltaSa:   pop,
deltaSb:   pop, -- Last two
kASource:  fpUnldMsw,
euPBusCmd:  FetchFPAlu ]];
Set[s: PO.And[dblBiAlu, state], out:[
dontGetNextMacro: FALSE,
deltaSa:   pop,
deltaSb:   pop,
cReg:    [ s, minus2 ],
kASource:  fpUnldLsw,
euPBusCmd:  FetchFPAlu ]];
Set[s: PO.And[dblBiMult, state], out:[
dontGetNextMacro: FALSE,
deltaSa:   pop,
deltaSb:   pop,
cReg:    [ s, minus2 ],
kASource:  fpUnldLsw,
euPBusCmd:  FetchFPAlu ]];
statePO.And[instr,  BE[m:[state: byteIsSig], d:[state: 9]]];
Set[s: PO.And[dblBiMult, state], out:[
dontGetNextMacro: FALSE,
deltaSa:   pop,
deltaSb:   pop,
cReg:    [ s, minus2 ],
kASource:  fpUnldLsw,
euPBusCmd:  FetchFPMult ]]};
GeneratePhBPLA3a[];
GeneratePhBPLA3b[];
GeneratePhBPLA4[] };
END.