IFUPLAFetchControlImpl.mesa
Copyright c 1984 by Xerox Corporation. All rights reserved.
Last edited by Curry, October 22, 1986 2:48:49 pm PDT
McCreight, June 6, 1986 6:11:48 pm PDT
Don Curry March 14, 1987 4:17:57 pm PST
DIRECTORY
Commander,
Dragon,
DragOpsCross,
IFUPLAFetchControl,
IO,
PLAOps;
IFUPLAFetchControlImpl:
CEDAR
PROGRAM
IMPORTS Commander, IO, PLAOps =
BEGIN OPEN PO: PLAOps;
FetchRdDecodePLA: PLAOps.PLA;
FetchWtDecodePLA: PLAOps.PLA;
FetchControlPLA: PLAOps.PLA;
FetchControlIn: TYPE = IFUPLAFetchControl.FetchControlIn;
FetchControlOut: TYPE = IFUPLAFetchControl.FetchControlOut;
FetchRdDecodeIn: TYPE = IFUPLAFetchControl.FetchRdDecodeIn;
FetchRdDecodeOut: TYPE = IFUPLAFetchControl.FetchRdDecodeOut;
FetchWtDecodeIn: TYPE = IFUPLAFetchControl.FetchWtDecodeIn;
FetchWtDecodeOut: TYPE = IFUPLAFetchControl.FetchWtDecodeOut;
JumpOffsetSel: TYPE = IFUPLAFetchControl.JumpOffsetSel;
GenFetchControlPLA:
PUBLIC
PROC = {
pBusFaultIsSig: Dragon.PBusFaults ← LAST [Dragon.PBusFaults];
jump: PO.BoolExpr ← BE[m:[nextMacroJump: TRUE], d:[nextMacroJump: TRUE]];
reset: PO.BoolExpr ← BE[m:[reset: TRUE], d:[reset: TRUE]];
reject: PO.BoolExpr ← BE[m:[iPReject: TRUE], d:[iPReject: TRUE]];
jumpPending: PO.BoolExpr ← BE[m:[jumpPendingIn: TRUE], d:[jumpPendingIn: TRUE]];
fetching: PO.BoolExpr ← BE[m:[fetchingIn: TRUE], d:[fetchingIn: TRUE]];
roomFor1: PO.BoolExpr ← PO.Not[BE[m:[fetchBytesM1: 28], d:[fetchBytesM1: 12]] ];
roomFor2: PO.BoolExpr ← PO.Not[BE[m:[fetchBytesM1: 24], d:[fetchBytesM1: 8]] ];
iPFaulted: PO.BoolExpr ← BE[m:[iPFaultedIn: TRUE], d:[iPFaultedIn: TRUE]];
newFault: PO.BoolExpr ← BE[m:[iPFaulting: TRUE], d:[iPFaulting: TRUE]];
jmpOrJmpPend: PO.BoolExpr ← PO.Or[jump, jumpPending];
roomForFetch:
PO.BoolExpr ←
PO.Or[roomFor2,
PO.And[
PO.Not[fetching], roomFor1]];
Set[out:[jumpPending:
TRUE],
s:PO.And[PO.Not[reset], PO.Not[iPFaulted], jmpOrJmpPend, reject ] ];
Set[out:[newFetch:
TRUE],
-- sets IPCmnd3A to Fetch in next A
s:
PO.And[
PO.Not[reset],
PO.Not[iPFaulted],
PO.Not[reject],
PO.Or[roomForFetch, jmpOrJmpPend] ] ];
Set[out:[fetching:
TRUE],
-- enables write in next B
s:
PO.And[
PO.Not[reset],
PO.Not[iPFaulted],
PO.Or[
PO.And[ reject, fetching],
PO.And[PO.Not[reject], roomForFetch],
PO.And[PO.Not[reject], jmpOrJmpPend] ] ] ];
Set[out:[iPFaulted:
TRUE],
s:
PO.Or[
reset,
PO.And[
PO.Not[jmpOrJmpPend],
PO.Or[iPFaulted, newFault] ] ] ];
Set[out:[fetchWtIndexCtl: clear], s: jmpOrJmpPend ];
Set[out:[fetchWtIndexCtl: hold],
s:
PO.And[
PO.Not[jmpOrJmpPend],
PO.Or[PO.Not[fetching], reject, iPFaulted] ] ];
Set[out:[fetchWtIndexCtl: inc],
s:
PO.And[
PO.Not[jmpOrJmpPend],
fetching,
PO.Not[reject],
PO.Not[iPFaulted] ] ];
GenPreDecode:
PUBLIC
PROC = {
SetJumpOffset:
PROC[inst: DragOpsCross.Inst, val: JumpOffsetSel] = {
op: INT [0..8) ← LOOPHOLE[inst, CARDINAL]/32;
IF NOT reservations[op].used THEN reservations[op] ← [TRUE, val];
IF reservations[op].val # val THEN ERROR;
Set[out:[jumpOffset: val], s: BE[m:[op: 7], d:[op: op]]] };
reservations: ARRAY [0..8) OF RECORD [used: BOOL ← FALSE, val: JumpOffsetSel�ta ];
op0: PO.BoolExpr ← BE[m:[op: 4], d:[op: 4]];
op1: PO.BoolExpr ← BE[m:[op: 2], d:[op: 2]];
op2: PO.BoolExpr ← BE[m:[op: 1], d:[op: 1]];
oneByter:
PO.BoolExpr ←
PO.Or[
PO.And[ PO.Not[op0], PO.Not[op1], PO.Not[op2] ],
PO.And[ PO.Not[op0], op1 ] ];
twoByter: PO.BoolExpr ← PO.And[ op0, PO.Not[op1] ];
threeByter: PO.BoolExpr ← PO.And[ op0, op1 ];
fiveByter: PO.BoolExpr ← PO.And[ PO.Not[op0], PO.Not[op1], op2 ];
bytesAvail0: PO.BoolExpr ← BE[m:[fetchBytesM1: 16], d:[fetchBytesM1: 16 ]];
bytesAvail1: PO.BoolExpr ← BE[m:[fetchBytesM1: 31], d:[fetchBytesM1: 0 ]];
bytesAvail2: PO.BoolExpr ← BE[m:[fetchBytesM1: 31], d:[fetchBytesM1: 1 ]];
bytesAvail3: PO.BoolExpr ← BE[m:[fetchBytesM1: 31], d:[fetchBytesM1: 2 ]];
bytesAvail4: PO.BoolExpr ← BE[m:[fetchBytesM1: 31], d:[fetchBytesM1: 3 ]];
notReady:
PO.BoolExpr ←
PO.Or[
bytesAvail0,
PO.And[ bytesAvail1, PO.Or[ twoByter, threeByter, fiveByter ] ],
PO.And[ bytesAvail2, PO.Or[ threeByter, fiveByter ] ],
PO.And[ PO.Or[ bytesAvail3, bytesAvail4 ], fiveByter ] ];
Set[out:[notInstReady: TRUE], s: notReady];
Set[out:[instFault0:TRUE], s:PO.And[notReady, BE[m:[iPFaulting:TRUE], d:[iPFaulting:TRUE]]]];
Set[out:[opLength: 5, opLengthb: 5], s: fiveByter ];
Set[out:[opLength: 1, opLengthb: 1], s: oneByter ];
Set[out:[opLength: 2, opLengthb: 2], s: twoByter ];
Set[out:[opLength: 3, opLengthb: 3], s: threeByter ];
SetJumpOffset[dJB, alpha];
SetJumpOffset[dJDB, alphaBeta];
SetJumpOffset[dLFC, alphaBeta];
SetJumpOffset[dJSR, xa];
FOR inst: DragOpsCross.Inst IN [dRJEB..dRJLEBJ] DO SetJumpOffset[inst, beta] ENDLOOP;
FOR inst: DragOpsCross.Inst IN [dJEBB..dJNEBBJ] DO SetJumpOffset[inst, beta] ENDLOOP};
GenFetchRdDecodePLA:
PROC = {
-- decode 0=>xxx.0=TRUE, 1=>xxx.1=TRUE
FOR fetchRd:
CARDINAL
IN [0..16)
DO
val: CARDINAL ← 1;
THROUGH (fetchRd..16) DO val ← val*2 ENDLOOP;
SetRd[m:[fetchRd: 15], d:[fetchRd: fetchRd], out:[fetchBufRdByte: val]];
ENDLOOP};
GenFetchWtDecodePLA:
PROC = {
-- decode 0=>xxx.0=TRUE, 1=>xxx.1=TRUE
FOR fetchWt:
CARDINAL
IN [0..4)
DO
val: CARDINAL ← 1;
THROUGH (fetchWt..4) DO val ← val*2 ENDLOOP;
SetWt[
m: [fetching: TRUE, fetchWt: 3],
d: [fetching:
TRUE, fetchWt: fetchWt],
out:[fetchBufWtWd: val]];
ENDLOOP};
BE:
PROC [m, d: FetchControlIn]
RETURNS[
PO.BoolExpr] = {
mRef: REF FetchControlIn ← NARROW[FetchControlPLA.mask];
dRef: REF FetchControlIn ← NARROW[FetchControlPLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PO.GetBEForDataMask[FetchControlPLA]]};
BER:
PROC [m, d: FetchRdDecodeIn]
RETURNS[PLAOps.BoolExpr] = {
mRef: REF FetchRdDecodeIn ← NARROW[FetchRdDecodePLA.mask];
dRef: REF FetchRdDecodeIn ← NARROW[FetchRdDecodePLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PLAOps.GetBEForDataMask[FetchRdDecodePLA]]};
BEW:
PROC [m, d: FetchWtDecodeIn]
RETURNS[PLAOps.BoolExpr] = {
mRef: REF FetchWtDecodeIn ← NARROW[FetchWtDecodePLA.mask];
dRef: REF FetchWtDecodeIn ← NARROW[FetchWtDecodePLA.data];
mRef^ ← m; dRef^ ← d; RETURN[PLAOps.GetBEForDataMask[FetchWtDecodePLA]]};
Set:
PROC [s:
PO.BoolExpr ←
NIL, m, d: FetchControlIn ← [ ], out: FetchControlOut] = {
res: REF FetchControlOut ← NARROW[FetchControlPLA.out];
IF s=
NIL
THEN s ← BE[m,d]
ELSE s ← PO.And[s, BE[m,d] ];
res^ ← out; PO.SetOutForBE[FetchControlPLA, s]};
SetRd:
PROC [s: PLAOps.BoolExpr ←
NIL, m, d: FetchRdDecodeIn ←[], out: FetchRdDecodeOut]={
res: REF FetchRdDecodeOut ← NARROW[FetchRdDecodePLA.out];
IF s=
NIL
THEN s ← BER[m,d]
ELSE s ← PLAOps.And[s, BER[m,d] ];
res^ ← out; PLAOps.SetOutForBE[FetchRdDecodePLA, s]};
SetWt:
PROC [s: PLAOps.BoolExpr ←
NIL, m, d: FetchWtDecodeIn←[], out: FetchWtDecodeOut]={
res: REF FetchWtDecodeOut ← NARROW[FetchWtDecodePLA.out];
IF s=
NIL
THEN s ← BEW[m,d]
ELSE s ← PLAOps.And[s, BEW[m,d] ];
res^ ← out; PLAOps.SetOutForBE[FetchWtDecodePLA, s]};
GenFetchControl: Commander.CommandProc = {
rdInType: IO.ROPE ← "IFUPLAFetchControl.FetchRdDecodeIn";
wtInType: IO.ROPE ← "IFUPLAFetchControl.FetchWtDecodeIn";
ctlInType: IO.ROPE ← "IFUPLAFetchControl.FetchControlIn";
FetchRdDecodePLA ← PO.NewPLA[rdInType, "IFUPLAFetchControl.FetchRdDecodeOut"];
FetchWtDecodePLA ← PO.NewPLA[wtInType, "IFUPLAFetchControl.FetchWtDecodeOut"];
FetchControlPLA ← PO.NewPLA[ctlInType, "IFUPLAFetchControl.FetchControlOut"];
GenFetchRdDecodePLA [];
GenFetchWtDecodePLA [];
GenFetchControlPLA [];
[] ←PO.ConvertTermListToCompleteSum[FetchRdDecodePLA.termList, FALSE,FALSE,cmd.out];
[] ←PO.ConvertTermListToCompleteSum[FetchWtDecodePLA.termList, FALSE,FALSE,cmd.out];
[] ←PO.ConvertTermListToCompleteSum[FetchControlPLA.termList, FALSE,FALSE,cmd.out];
[] ←PO.FindAMinimalCover[FetchRdDecodePLA.termList, 120, cmd.out];
[] ←PO.FindAMinimalCover[FetchWtDecodePLA.termList, 120, cmd.out];
[] ←PO.FindAMinimalCover[FetchControlPLA.termList, 120, cmd.out];
PO.WritePLAFile[ "IFUPLAFetchRdDecode.ttt", cmd.out, FetchRdDecodePLA];
PO.WritePLAFile[ "IFUPLAFetchWtDecode.ttt", cmd.out, FetchWtDecodePLA];
PO.WritePLAFile[ "IFUPLAFetchControl.ttt", cmd.out, FetchControlPLA] };
defaultFile: IO.ROPE = "IFUPLAFetchControl.ttt";
doc: IO.ROPE = "Expects the name of a ttt file";
Commander.Register[key:"GenFetchControl", proc: GenFetchControl, doc: doc];
END.