
<<IFUPLA.mesa>>
<<Copyright © 1984 by Xerox Corporation.  All rights reserved.>>
<<Last edited by Twilliams, August 27, 1984 6:28:59 pm PDT>>
<<Last edited by Curry, January 28, 1985 11:32:06 am PST>>

DIRECTORY
Basics,
Dragon,
DragOpsCross,
IO,
PLAOps;

IFUPLA: CEDAR DEFINITIONS IMPORTS Basics =
BEGIN

MainControlProc:         PROC[args: MainControlIn]     RETURNS[result: MainControlOut];
InstrDecodeProc:         PROC[args: InstrDecodeIn]         RETURNS[result: InstrDecodeOut];
FetchControlProc:     PROC[args: FetchControlIn]     RETURNS[result: FetchControlOut];
FetchPreDecodeProc:     PROC[args: FetchPreDecodeIn]  RETURNS[result: FetchPreDecodeOut];

MainControlIn: TYPE = RECORD [    -- default must be zero for use initializing sigificance arg
reseting:                BOOL                    _  FALSE,
wereReseting:        BOOL                    _  FALSE,

epFaulted:            BOOL                    _  FALSE,
fpFaulted:            BOOL                    _  FALSE,
epRejected:            BOOL                    _  FALSE,

euCondition:            BOOL                    _  FALSE,
euCondEffect2:        CondEffect            _  LOOPHOLE[0],

epCmndRd1Rd:        BOOL                    _  FALSE,
epCmndRd2Rd:        BOOL                    _  FALSE,
kIsRtOp:                BOOL                    _  FALSE,
passingRt:            BOOL                    _  FALSE,
fieldInterlock:        BOOL                    _  FALSE,

aRegIsC2:                BOOL                    _  FALSE,
aRegIsC3:                BOOL                    _  FALSE,
bRegIsC2:                BOOL                    _  FALSE,
bRegIsC3:                BOOL                    _  FALSE,

getNextInst:            BOOL                    _  FALSE,
macroJump:            BOOL                    _  FALSE,
ipFaulted:            BOOL                    _  FALSE,
trapsEnbled:            BOOL                    _  FALSE,
rschlWaiting:        BOOL                    _  FALSE,
iStkOverflow:        BOOL                    _  FALSE,
eStkOverFlow:        BOOL                    _  FALSE,
pushPending:        BOOL                    _  FALSE,
popPending:            BOOL                    _  FALSE ];

MainControlOut: TYPE = RECORD [
microFixedJump:        BOOL _ FALSE,        -- IF microBranch, MicroCycle _ fixedMicroJump
exception:            BOOL _ FALSE,
exceptionCode:        ExceptionCode _ 0,    -- IF exception, MicroCycle _ exceptionCode

pipeCycle0:            BOOL _ FALSE,
pipeCycle123:        BOOL _ FALSE,
pipeKill1:                BOOL _ FALSE,
pipeKill2:                BOOL _ FALSE,
pipeCCTrap3:            BOOL _ FALSE,
pipeFault3:            BOOL _ FALSE,

aluLt:                    Dragon.ALULeftSources    _ aBus,
aluRt:                    Dragon.ALURightSources    _ bBus,
st2A:                    Dragon.Store2ASources        _ bBus,
st3AIsCbus:            BOOL _ FALSE,
res3AIsCbus:            BOOL _ FALSE,
res3BIsRdData:        BOOL _ FALSE
];

InstrDecodeIn: TYPE = RECORD [    -- default must be zero for use initializing sigificance arg

state:                Dragon.HexByte _ 0,
pipeCycle0:        BOOL _ FALSE,
instReady:        BOOL _ FALSE,
op:                DragOpsCross.Inst _ LOOPHOLE[0],
alpha:                Dragon.HexByte _ 0,
beta:                Dragon.HexByte _ 0,
fpEnabled:        BOOL _ FALSE,
iStkEmpty:        BOOL _ FALSE,
pushPending:    BOOL _ FALSE,
popPending:        BOOL _ FALSE,
userMode:        BOOL _ FALSE ];

InstrDecodeOut: TYPE = RECORD [
instrDelayed:            BOOL                            _ FALSE,
microJump:            BOOL                            _ FALSE,
macroJump:            BOOL                            _ FALSE,
dontGetNextMacro:    BOOL                            _ FALSE,
setStatusFrom3Lev:     BOOL                            _ FALSE,
pcBusSrc:                PCBusSrc                        _ pc,
pclsPipeSrc:            PCLSPipeSrc                    _ old,
push:                    BOOL                            _ FALSE,
pop:                    BOOL                            _ FALSE,

aReg:                    ABReg                        _ constantZero,
bReg:                    ABReg                        _ constantZero,
cReg:                    CReg                            _ inhibitStore,
lSource:                LSource                        _ [ l, zero ],
sSource:                SSource                        _ [ s, deltaS ],
popSa:                    BOOL                            _ FALSE,
popSb:                BOOL                            _ FALSE,
pushSc:                BOOL                            _ FALSE,

xaSource:                XaSource                        _ none,
kIsRtOp:                BOOL                            _ FALSE,

aluOp:                Dragon.ALUOps                _ Or,
aluOpIsOp47:            BOOL                            _ FALSE,
condSel:                Dragon.CondSelects            _ False,
condSelIsOp57:        BOOL                            _ FALSE,
condEffect:            CondEffect                    _ macroTrap,
notPassRtIfAZero:    BOOL                            _ FALSE,
epCmnd:                Dragon.PBusCommands        _ NoOp,
fpCheckStatus:        BOOL                            _ FALSE,

clearTrapsEnbled:        BOOL                        _ FALSE,
clearUserMode:            BOOL                        _ FALSE
];

DefaultMicro:    InstrDecodeOut = [];
NoOpMicro:        InstrDecodeOut = [dontGetNextMacro: TRUE];
Delayed:            InstrDecodeOut = [
dontGetNextMacro:    TRUE,
pclsPipeSrc:            holdLastEntry,
instrDelayed:            TRUE];
Trap:                InstrDecodeOut = [
macroJump:            TRUE,
dontGetNextMacro:    TRUE,
pcBusSrc:                trapGen, 
push:                    TRUE,
clearTrapsEnbled:    TRUE ];
SingleByteXop:    InstrDecodeOut    = [
macroJump:            TRUE,
dontGetNextMacro:    TRUE,
pcBusSrc:                xopGen,
pclsPipeSrc:            seqPCnewLS,
push:                    TRUE ];
MultiByteXop:    InstrDecodeOut    = [
macroJump:            TRUE,
dontGetNextMacro:    TRUE,
pcBusSrc:                xopGen,
pclsPipeSrc:            seqPCnewLS,
push:                    TRUE,
xaSource:                delGamBetAlp,
cReg:                    [s, one],
pushSc:                TRUE ];

FetchControlIn: TYPE = RECORD [    -- default must be zero for use initializing sigificance arg
jump:                BOOL _ FALSE,
getNext:            BOOL _ FALSE,
hold:                BOOL _ FALSE,
reject:                BOOL _ FALSE,
jumping:            BOOL _ FALSE,
jumpInProgress:    BOOL _ FALSE,
jumpPending:    BOOL _ FALSE,
fetching:            BOOL _ FALSE,
roomFor1:            BOOL _ FALSE,
roomFor2:            BOOL _ FALSE,
faulted:            BOOL _ FALSE,
ipPageFault:        BOOL _ FALSE,
opLength:        [0..7] _  LOOPHOLE[0],
offSet:                [0..3] _  LOOPHOLE[0]
];

FetchControlOut: TYPE = RECORD [-- default must be zero
jumpInProgress:    BOOL _ FALSE,
jumpPending:    BOOL _ FALSE,
newFetch:        BOOL _ FALSE,
fetching:            BOOL _ FALSE,
faulted:            BOOL _ FALSE,
incrPrefetch:        BOOL _ FALSE,
wt:                WtIndexCtl    _ [ ],
rd:                    RdIndexCtl    _ [ ]
];

FetchPreDecodeIn: TYPE = RECORD [    -- default must be zero
preOp:        DragOpsCross.Inst _ LOOPHOLE[0],
atLeast1:        BOOL _ FALSE,
atLeast2:        BOOL _ FALSE,
atLeast3:        BOOL _ FALSE,
atLeast5:        BOOL _ FALSE
];

FetchPreDecodeOut: TYPE = RECORD [-- default must be zero
notInstReady:        BOOL _ FALSE,
opLength:            [0..7] _ 0
];

WtIndexCtl: TYPE = RECORD[
set0:    BOOL _ FALSE,
inc0:    BOOL _ FALSE,
inc1:    BOOL _ FALSE ];

RdIndexCtl: TYPE = RECORD[
set0:    BOOL _ FALSE,
set1:    BOOL _ FALSE,
set2:    BOOL _ FALSE,
set3:    BOOL _ FALSE,
inc0:    BOOL _ FALSE,
inc1:    BOOL _ FALSE,
inc2:    BOOL _ FALSE,
inc3:    BOOL _ FALSE,
inc5:    BOOL _ FALSE ];

fixedMicroJump: Dragon.HexByte = 64;

ExceptionCode: TYPE = Dragon.HexByte;    --    excep trapQuad index
none            :ExceptionCode    = 000B;    --        00        00        0000   default trap underFlow
ipFault        :ExceptionCode    = 201B;    --        10        00        0100 
reset            :ExceptionCode    = 202B;    --        10        00        1000
reseting        :ExceptionCode    = 203B;    --        10        00        1100
cJump        :ExceptionCode    = 204B;    --     10        00        0101
iStkOFlow    :ExceptionCode    = 210B;    --        10        00        0001
eStkOFlow    :ExceptionCode    = 211B;    --        10        00        0010
rschlWait        :ExceptionCode    = 212B;    --     10        00        0011
cTrap            :ExceptionCode    = 220B;    --        10        01        0000    use CCSelCode as index
fpFault        :ExceptionCode    = 240B;    --        10        10        0000    use PBusFault as index
epFault        :ExceptionCode    = 260B;    --        10        11        0000    use PBusFault as index

CondEffect: TYPE = MACHINE DEPENDENT {macroTrap(0),macroJump,microJump,res(3)};
useBeta47: Dragon.PBusCommands = Reserve1;

PCBusSrc: TYPE = MACHINE DEPENDENT
{pc(0), offSetPC, stack, delGamBetAlp, xA, pipe3, trapGen, xopGen};
PCLSPipeSrc: TYPE = MACHINE DEPENDENT
{old(0), seqPCnewLS(1), offSetPCnewLS(2), holdLastEntry(3)};

<<This is essentially the Load-Unload code for the Weitek chips with alpha-beta-gamma-delta selection stuck into gaps in the 
encoding.  See DragonIFU33.sil>>
<<Note: alpha-beta-gamma-delta selection must => DrXa2>>
XaSource:            TYPE = MACHINE DEPENDENT {
none(00B),
fpLdSglBSt(06B),
fpLdLswB(10B),            fpLdLswBSt(12B),        fpLdMswB(14B),        fpLdMswBSt(16B),
delGamBetAlp(20B),        betaAlpha(21B),            beta(22B),                    alpha(23B),
fpLdSglAUnMsw(25B),    fpLdLswAUnLsw(30B),    fpLdMswAUnMsw(35B),    res31(37B)};

ABReg:        TYPE = RECORD [ lt: ABSourceLt, rt: ABSourceRt ]; -- 7 bits
ABSourceLt:    TYPE = MACHINE DEPENDENT {cBase(0), aBase, s, l, iRef, zero};
ABSourceRt:    TYPE = MACHINE DEPENDENT {
zero(0),        one(1),        two(2),        three(3),
minus4(4),    minus3(5),    minus2(6),    minus1(7),
op47(8),        alpha(9),        alpha03(10),    alpha47(11),
deltaS(12),    beta(13),        beta03(14),    beta47(15)};
CReg: TYPE = RECORD [ lt: CSourceLt, rt: CSourceRt ]; -- 7 bits
CSourceLt:    TYPE = MACHINE DEPENDENT {fpAlu(0), fpMult, aBase, cBase, zero, l, s, iRef};
CSourceRt:    TYPE = MACHINE DEPENDENT {-- addr bit 1 invrtd from ABSourceRt
minus4(0),    minus3(1),    minus2(2),    minus1(3),
zero(4),        one(5),        two(6),        three(7),
deltaS(8),        beta(9),        beta03(10),    beta47(11),
op47(12),        alpha(13),    alpha03(14),    alpha47(15)};

LSource: TYPE = RECORD [ lt: LSourceLt, rt: LSourceRt ]; -- 4 bits
LSourceLt:            TYPE = MACHINE DEPENDENT {l(0), s, zero, l3};
LSourceRt:            TYPE = MACHINE DEPENDENT { zero(0), alpha, stack, one};
SSource: TYPE = RECORD [ lt: SSourceLt, rt: SSourceRt ]; -- 4 bits
SSourceLt:            TYPE = MACHINE DEPENDENT {s(0), l, zero, s3};
SSourceRt:            TYPE = MACHINE DEPENDENT { deltaS(0), alpha, zero, one};

<<These must agree with DragOpsCross.ProcessorRegister>>
abStackTop:        ABReg    = [ s      , zero ];
cStackTop:        CReg        = [ s      , zero ];
constantZero:        ABReg    = [ cBase , zero ];
euGF:                ABReg    = [ aBase , zero ];
ifuStatusABReg:    ABReg    = [ iRef  , one ];
inhibitStore:        CReg        = [ fpAlu , minus4 ];
euField:            CReg        = [ fpAlu , minus1 ];
fpAluClr:            CReg        = [ fpAlu , zero ];
fpAluSgl:            CReg        = [ fpAlu , one ];
fpAluLsw:        CReg        = [ fpAlu , two ];
fpAluMsw:        CReg        = [ fpAlu , three ];
fpMultClr:        CReg        = [ fpMult , zero ];
fpMultSgl:        CReg        = [ fpMult , one ];
fpMultLsw:        CReg        = [ fpMult , two ];
fpMultMsw:        CReg        = [ fpMult , three ];
ifuXBus:            CReg        = [ iRef  , zero ];
ifuStatus:            CReg        = [ iRef  , one ];
ifuFPModeAlu:    CReg        = [ iRef  , two ];
ifuFPModeMult:    CReg        = [ iRef  , three ];

ByteTopSig: PROC[topBits: CARDINAL] RETURNS[byte: Dragon.HexByte] = INLINE
{RETURN[Basics.BITAND[Basics.BITSHIFT[377B, (8-topBits)], 377B]]};

InstrTopSig: PROC[topBits: CARDINAL] RETURNS[DragOpsCross.Inst] = INLINE
{RETURN[LOOPHOLE[ByteTopSig[topBits]]]};

<<Used by InstrDecode>>
current:                        PLAOps.BoolExpr;
GenInstrDecodePLA1:    PROC;
GenInstrDecodePLA2:    PROC;
GenInstrDecodePLA3:    PROC;
GenInstrDecodePLA4:    PROC;
GenInstrDecodePLA5:    PROC;
BE:    PROC [m, d: InstrDecodeIn] RETURNS[PLAOps.BoolExpr];
Set:    PROC [s: PLAOps.BoolExpr _ NIL, m, d: InstrDecodeIn _ [ ], out: InstrDecodeOut];

ControlPipeRec: TYPE = RECORD [    -- ~35 bits - This is an aid to the ControlPipe Rose sim
drXa2Lev:        BOOL                            _ FALSE,
drXa3Lev:        BOOL                            _ FALSE,
push:                BOOL                            _ FALSE,
pop:                BOOL                            _ FALSE,
epCmnd:            Dragon.PBusCommands        _ NoOp,
fpCSUnAlu:        BOOL                            _ FALSE,
fpCSUnMult:        BOOL                            _ FALSE,
fpCheckStatus:    BOOL                            _ FALSE,
fpCSLdAlu:        BOOL                            _ FALSE,
fpCSLdMult:        BOOL                            _ FALSE,
aluLeftSrc:        Dragon.ALULeftSources    _ aBus,
aluRightSrc:        Dragon.ALURightSources    _ bBus,
store2ASrc:        Dragon.Store2ASources        _ bBus,
aluOp:            Dragon.ALUOps                _ Or,
condSel:            Dragon.CondSelects            _ False,
st3AisCBus:        BOOL                            _ FALSE,
res3AisCBus:        BOOL                            _ FALSE,
condEffect:        CondEffect                    _ macroTrap,
checkParity:        BOOL                            _ FALSE,
writeToPBus:        BOOL                            _ FALSE,
res3BisPBus:        BOOL                            _ FALSE ];

END.