IFUPLA:
CEDAR
DEFINITIONS
IMPORTS Basics =
BEGIN
MainControlProc: PROC[args: MainControlIn] RETURNS[result: MainControlOut];
InstrDecodeProc: PROC[args: InstrDecodeIn] RETURNS[result: InstrDecodeOut];
FetchControlProc: PROC[args: FetchControlIn] RETURNS[result: FetchControlOut];
FetchPreDecodeProc: PROC[args: FetchPreDecodeIn] RETURNS[result: FetchPreDecodeOut];
MainControlIn:
TYPE =
RECORD [
-- default must be zero for use initializing sigificance arg
reseting: BOOL ← FALSE,
wereReseting: BOOL ← FALSE,
epFaulted: BOOL ← FALSE,
fpFaulted: BOOL ← FALSE,
epRejected: BOOL ← FALSE,
euCondition: BOOL ← FALSE,
euCondEffect2: CondEffect ← LOOPHOLE[0],
epCmndRd1Rd: BOOL ← FALSE,
epCmndRd2Rd: BOOL ← FALSE,
kIsRtOp: BOOL ← FALSE,
passingRt: BOOL ← FALSE,
fieldInterlock: BOOL ← FALSE,
aRegIsC2: BOOL ← FALSE,
aRegIsC3: BOOL ← FALSE,
bRegIsC2: BOOL ← FALSE,
bRegIsC3: BOOL ← FALSE,
getNextInst: BOOL ← FALSE,
macroJump: BOOL ← FALSE,
ipFaulted: BOOL ← FALSE,
trapsEnbled: BOOL ← FALSE,
rschlWaiting: BOOL ← FALSE,
iStkOverflow: BOOL ← FALSE,
eStkOverFlow: BOOL ← FALSE,
pushPending: BOOL ← FALSE,
popPending: BOOL ← FALSE ];
MainControlOut:
TYPE =
RECORD [
microFixedJump: BOOL ← FALSE, -- IF microBranch, MicroCycle ← fixedMicroJump
exception: BOOL ← FALSE,
exceptionCode: ExceptionCode ← 0, -- IF exception, MicroCycle ← exceptionCode
pipeCycle0: BOOL ← FALSE,
pipeCycle123: BOOL ← FALSE,
pipeKill1: BOOL ← FALSE,
pipeKill2: BOOL ← FALSE,
pipeCCTrap3: BOOL ← FALSE,
pipeFault3: BOOL ← FALSE,
aluLt: Dragon.ALULeftSources ← aBus,
aluRt: Dragon.ALURightSources ← bBus,
st2A: Dragon.Store2ASources ← bBus,
st3AIsCbus: BOOL ← FALSE,
res3AIsCbus: BOOL ← FALSE,
res3BIsRdData: BOOL ← FALSE
];
InstrDecodeIn:
TYPE =
RECORD [
-- default must be zero for use initializing sigificance arg
state: Dragon.HexByte ← 0,
pipeCycle0: BOOL ← FALSE,
instReady: BOOL ← FALSE,
op: DragOpsCross.Inst ← LOOPHOLE[0],
alpha: Dragon.HexByte ← 0,
beta: Dragon.HexByte ← 0,
fpEnabled: BOOL ← FALSE,
iStkEmpty: BOOL ← FALSE,
pushPending: BOOL ← FALSE,
popPending: BOOL ← FALSE,
userMode: BOOL ← FALSE ];
InstrDecodeOut:
TYPE =
RECORD [
instrDelayed: BOOL ← FALSE,
microJump: BOOL ← FALSE,
macroJump: BOOL ← FALSE,
dontGetNextMacro: BOOL ← FALSE,
setStatusFrom3Lev: BOOL ← FALSE,
pcBusSrc: PCBusSrc ← pc,
pclsPipeSrc: PCLSPipeSrc ← old,
push: BOOL ← FALSE,
pop: BOOL ← FALSE,
aReg: ABReg ← constantZero,
bReg: ABReg ← constantZero,
cReg: CReg ← inhibitStore,
lSource: LSource ← [ l, zero ],
sSource: SSource ← [ s, deltaS ],
popSa: BOOL ← FALSE,
popSb: BOOL ← FALSE,
pushSc: BOOL ← FALSE,
xaSource: XaSource ← none,
kIsRtOp: BOOL ← FALSE,
aluOp: Dragon.ALUOps ← Or,
aluOpIsOp47: BOOL ← FALSE,
condSel: Dragon.CondSelects ← False,
condSelIsOp57: BOOL ← FALSE,
condEffect: CondEffect ← macroTrap,
notPassRtIfAZero: BOOL ← FALSE,
epCmnd: Dragon.PBusCommands ← NoOp,
fpCheckStatus: BOOL ← FALSE,
clearTrapsEnbled: BOOL ← FALSE,
clearUserMode: BOOL ← FALSE
];
DefaultMicro: InstrDecodeOut = [];
NoOpMicro: InstrDecodeOut = [dontGetNextMacro: TRUE];
Delayed: InstrDecodeOut = [
dontGetNextMacro: TRUE,
pclsPipeSrc: holdLastEntry,
instrDelayed: TRUE];
Trap: InstrDecodeOut = [
macroJump: TRUE,
dontGetNextMacro: TRUE,
pcBusSrc: trapGen,
push: TRUE,
clearTrapsEnbled: TRUE ];
SingleByteXop: InstrDecodeOut = [
macroJump: TRUE,
dontGetNextMacro: TRUE,
pcBusSrc: xopGen,
pclsPipeSrc: seqPCnewLS,
push: TRUE ];
MultiByteXop: InstrDecodeOut = [
macroJump: TRUE,
dontGetNextMacro: TRUE,
pcBusSrc: xopGen,
pclsPipeSrc: seqPCnewLS,
push: TRUE,
xaSource: delGamBetAlp,
cReg: [s, one],
pushSc: TRUE ];
Fetch
ControlIn:
TYPE =
RECORD [
-- default must be zero for use initializing sigificance arg
jump: BOOL ← FALSE,
getNext: BOOL ← FALSE,
hold: BOOL ← FALSE,
reject: BOOL ← FALSE,
jumping: BOOL ← FALSE,
jumpInProgress: BOOL ← FALSE,
jumpPending: BOOL ← FALSE,
fetching: BOOL ← FALSE,
roomFor1: BOOL ← FALSE,
roomFor2: BOOL ← FALSE,
faulted: BOOL ← FALSE,
ipPageFault: BOOL ← FALSE,
opLength: [0..7] ← LOOPHOLE[0],
offSet: [0..3] ← LOOPHOLE[0]
];
FetchControlOut:
TYPE =
RECORD [
-- default must be zero
jumpInProgress: BOOL ← FALSE,
jumpPending: BOOL ← FALSE,
newFetch: BOOL ← FALSE,
fetching: BOOL ← FALSE,
faulted: BOOL ← FALSE,
incrPrefetch: BOOL ← FALSE,
wt: WtIndexCtl ← [ ],
rd: RdIndexCtl ← [ ]
];
Fetch
PreDecodeIn:
TYPE =
RECORD [
-- default must be zero
preOp: DragOpsCross.Inst ← LOOPHOLE[0],
atLeast1: BOOL ← FALSE,
atLeast2: BOOL ← FALSE,
atLeast3: BOOL ← FALSE,
atLeast5: BOOL ← FALSE
];
FetchPreDecodeOut:
TYPE =
RECORD [
-- default must be zero
notInstReady: BOOL ← FALSE,
opLength: [0..7] ← 0
];
WtIndexCtl:
TYPE =
RECORD[
set0: BOOL ← FALSE,
inc0: BOOL ← FALSE,
inc1: BOOL ← FALSE ];
RdIndexCtl:
TYPE =
RECORD[
set0: BOOL ← FALSE,
set1: BOOL ← FALSE,
set2: BOOL ← FALSE,
set3: BOOL ← FALSE,
inc0: BOOL ← FALSE,
inc1: BOOL ← FALSE,
inc2: BOOL ← FALSE,
inc3: BOOL ← FALSE,
inc5: BOOL ← FALSE ];
fixedMicroJump: Dragon.HexByte = 64;
ExceptionCode:
TYPE = Dragon.HexByte; -- excep trapQuad index
none :ExceptionCode = 000B; -- 00 00 0000 default trap underFlow
ipFault :ExceptionCode = 201B; -- 10 00 0100
reset :ExceptionCode = 202B; -- 10 00 1000
reseting :ExceptionCode = 203B; -- 10 00 1100
cJump :ExceptionCode = 204B; -- 10 00 0101
iStkOFlow :ExceptionCode = 210B; -- 10 00 0001
eStkOFlow :ExceptionCode = 211B; -- 10 00 0010
rschlWait :ExceptionCode = 212B; -- 10 00 0011
cTrap :ExceptionCode = 220B; -- 10 01 0000 use CCSelCode as index
fpFault :ExceptionCode = 240B; -- 10 10 0000 use PBusFault as index
epFault :ExceptionCode = 260B; -- 10 11 0000 use PBusFault as index
CondEffect: TYPE = MACHINE DEPENDENT {macroTrap(0),macroJump,microJump,res(3)};
useBeta47: Dragon.PBusCommands = Reserve1;
PCBusSrc:
TYPE =
MACHINE
DEPENDENT
{pc(0), offSetPC, stack, delGamBetAlp, xA, pipe3, trapGen, xopGen};
PCLSPipeSrc:
TYPE =
MACHINE
DEPENDENT
{old(0), seqPCnewLS(1), offSetPCnewLS(2), holdLastEntry(3)};
This is essentially the Load-Unload code for the Weitek chips with alpha-beta-gamma-delta selection stuck into gaps in the encoding. See DragonIFU33.sil
Note: alpha-beta-gamma-delta selection must => DrXa2
XaSource:
TYPE =
MACHINE
DEPENDENT {
none(00B),
fpLdSglBSt(06B),
fpLdLswB(10B), fpLdLswBSt(12B), fpLdMswB(14B), fpLdMswBSt(16B),
delGamBetAlp(20B), betaAlpha(21B), beta(22B), alpha(23B),
fpLdSglAUnMsw(25B), fpLdLswAUnLsw(30B), fpLdMswAUnMsw(35B), res31(37B)};
ABReg: TYPE = RECORD [ lt: ABSourceLt, rt: ABSourceRt ]; -- 7 bits
ABSourceLt: TYPE = MACHINE DEPENDENT {cBase(0), aBase, s, l, iRef, zero};
ABSourceRt:
TYPE =
MACHINE
DEPENDENT {
zero(0), one(1), two(2), three(3),
minus4(4), minus3(5), minus2(6), minus1(7),
op47(8), alpha(9), alpha03(10), alpha47(11),
deltaS(12), beta(13), beta03(14), beta47(15)};
CReg: TYPE = RECORD [ lt: CSourceLt, rt: CSourceRt ]; -- 7 bits
CSourceLt: TYPE = MACHINE DEPENDENT {fpAlu(0), fpMult, aBase, cBase, zero, l, s, iRef};
CSourceRt:
TYPE =
MACHINE
DEPENDENT {
-- addr bit 1 invrtd from ABSourceRt
minus4(0), minus3(1), minus2(2), minus1(3),
zero(4), one(5), two(6), three(7),
deltaS(8), beta(9), beta03(10), beta47(11),
op47(12), alpha(13), alpha03(14), alpha47(15)};
LSource: TYPE = RECORD [ lt: LSourceLt, rt: LSourceRt ]; -- 4 bits
LSourceLt: TYPE = MACHINE DEPENDENT {l(0), s, zero, l3};
LSourceRt: TYPE = MACHINE DEPENDENT { zero(0), alpha, stack, one};
SSource: TYPE = RECORD [ lt: SSourceLt, rt: SSourceRt ]; -- 4 bits
SSourceLt: TYPE = MACHINE DEPENDENT {s(0), l, zero, s3};
SSourceRt: TYPE = MACHINE DEPENDENT { deltaS(0), alpha, zero, one};
These must agree with DragOpsCross.ProcessorRegister
abStackTop: ABReg = [ s , zero ];
cStackTop: CReg = [ s , zero ];
constantZero: ABReg = [ cBase , zero ];
euGF: ABReg = [ aBase , zero ];
ifuStatusABReg: ABReg = [ iRef , one ];
inhibitStore: CReg = [ fpAlu , minus4 ];
euField: CReg = [ fpAlu , minus1 ];
fpAluClr: CReg = [ fpAlu , zero ];
fpAluSgl: CReg = [ fpAlu , one ];
fpAluLsw: CReg = [ fpAlu , two ];
fpAluMsw: CReg = [ fpAlu , three ];
fpMultClr: CReg = [ fpMult , zero ];
fpMultSgl: CReg = [ fpMult , one ];
fpMultLsw: CReg = [ fpMult , two ];
fpMultMsw: CReg = [ fpMult , three ];
ifuXBus: CReg = [ iRef , zero ];
ifuStatus: CReg = [ iRef , one ];
ifuFPModeAlu: CReg = [ iRef , two ];
ifuFPModeMult: CReg = [ iRef , three ];
ByteTopSig:
PROC[topBits:
CARDINAL]
RETURNS[byte: Dragon.HexByte] =
INLINE
{RETURN[Basics.BITAND[Basics.BITSHIFT[377B, (8-topBits)], 377B]]};
InstrTopSig:
PROC[topBits:
CARDINAL]
RETURNS[DragOpsCross.Inst] =
INLINE
{RETURN[LOOPHOLE[ByteTopSig[topBits]]]};
Used by InstrDecode
current: PLAOps.BoolExpr;
GenInstrDecodePLA1: PROC;
GenInstrDecodePLA2: PROC;
GenInstrDecodePLA3: PROC;
GenInstrDecodePLA4: PROC;
GenInstrDecodePLA5: PROC;
BE: PROC [m, d: InstrDecodeIn] RETURNS[PLAOps.BoolExpr];
Set: PROC [s: PLAOps.BoolExpr ← NIL, m, d: InstrDecodeIn ← [ ], out: InstrDecodeOut];
ControlPipeRec:
TYPE =
RECORD [
-- ~35 bits - This is an aid to the ControlPipe Rose sim
drXa2Lev: BOOL ← FALSE,
drXa3Lev: BOOL ← FALSE,
push: BOOL ← FALSE,
pop: BOOL ← FALSE,
epCmnd: Dragon.PBusCommands ← NoOp,
fpCSUnAlu: BOOL ← FALSE,
fpCSUnMult: BOOL ← FALSE,
fpCheckStatus: BOOL ← FALSE,
fpCSLdAlu: BOOL ← FALSE,
fpCSLdMult: BOOL ← FALSE,
aluLeftSrc: Dragon.ALULeftSources ← aBus,
aluRightSrc: Dragon.ALURightSources ← bBus,
store2ASrc: Dragon.Store2ASources ← bBus,
aluOp: Dragon.ALUOps ← Or,
condSel: Dragon.CondSelects ← False,
st3AisCBus: BOOL ← FALSE,
res3AisCBus: BOOL ← FALSE,
condEffect: CondEffect ← macroTrap,
checkParity: BOOL ← FALSE,
writeToPBus: BOOL ← FALSE,
res3BisPBus: BOOL ← FALSE ];
END.