Imports IO, Dragon, DragonFP;
FPDevice: LAMBDA [type: |FPDeviceType|] RETURN CELLTYPE AutoName
PORTS [
CSLd3AB < EnumType["DragonFP.CSLoad"],
CSUn2AB < EnumType["DragonFP.CSUnload"],
EPFaultB > EnumType["Dragon.PBusFaults"],
EPData = INT[32], -- X in during A, Z out during B
KBus = INT[32], -- F, L, U in during A
PhA, PhB < BOOL,
InstrCountAB < INT[32] -- For log
]
State -- All state changes on down edge of PhA (ie are BA signals)
f0, f1, freg: DragonFP.Function,
mode: DragonFP.Mode,
x0, x1: Dragon.HexWord,
aM, aL, bM, bL: Dragon.HexWord,
arM, arL, brM, brL: Dragon.HexWord,
aluCSL1, mulCSL1: DragonFP.CSLoad,
aluCSU1, mulCSU1: DragonFP.CSUnload,
aluCSU2, mulCSU2: DragonFP.CSUnload,
load0, load1: DragonFP.Load,
unload0, unload1: DragonFP.Unload,
aluST0, mulST0: Dragon.PBusFaults,
aluST1, mulST1: Dragon.PBusFaults,
aluDM, mulDM: Dragon.HexWord,
aluDL, mulDL: Dragon.HexWord,
aluZ, mulZ: Dragon.HexWord
EvalSimple
IF PhA THEN {
clocked _ FALSE;
load0 _ LOOPHOLE[BitOps.ECFD[KBus, 32, 16+ 2, 5]];
f0 _ LOOPHOLE[BitOps.ECFD[KBus, 32, 16+ 7, 1]];
unload0 _ LOOPHOLE[BitOps.ECFD[KBus, 32, 16+10, 6]];
x0 _ Dragon.LFD[EPData];
};
IF NOT PhA AND NOT clocked THEN {
clocked _ TRUE;
cycle _ MAX[cycle-1, -1]; -- off at -1
IF cycle=0 THEN
csU2 _ csU1;
SELECT type FROM
Alu => [[aluDM, aluDL], aluST0] _
DragonFP.ALU [[arM,arL], [brM,brL], freg, mode, aArg, bArg];
Mult => [[mulDM, mulDL], mulST0] _
DragonFP.MUL [[arM,arL], [brM,brL], freg, mode, aArg, bArg];
csU1 _ CSUn2AB;
IF CSUn2AB=unload THEN
SELECT code FROM
fpLdSglAUnMsw => {ibus _ dm};
fpLdLswAUnLsw => {ibus _ dl};
fpLdMswAUnMsw => {ibus _ dm};
ENDCASE => Dragon.Assert[FALSE, "Unimplemented unload code"] };
IF CSLd3AB=load THEN {
SELECT code FROM
fpLdSglBSt => {brS _ ibus; freg_f1; start_TRUE};
fpLdLswB => {brL _ ibus; start_FALSE};
fpLdLswBSt => {brL _ ibus; freg_f1; start_TRUE};
fpLdMswB => {brM _ ibus; start_FALSE};
fpLdMswBSt => {brM _ ibus; freg_f1; start_TRUE};
fpLdSglAUnMsw => {arS _ ibus; unload_msw; start_FALSE};
fpLdLswAUnLsw => {arL _ ibus; unload_lsw; start_FALSE};
fpLdMswAUnMsw => {arM _ ibus; unload_msw; start_FALSE};
delGamBetAlp => mode _ DragonFP.SetMode[mode, f1];
ENDCASE => Dragon.Assert[FALSE, "Unimplemented load code"] };
aluZ _ IF unload1=msw THEN aluDM ELSE aluDL;
mulZ _ IF unload1=msw THEN mulDM ELSE mulDL;
unload1 _ unload0;
aluST1 _ aluST0;
mulST1 _ mulST0;
IF mulCSL1=load THEN { };
SELECT load1 FROM
none => { };
func => {arM_aM; arL_aL; brM_bM; brL_bL; freg_f1};
bLo => {arM_aM; arL_aL; brM_bM; brL_bL_x1; freg_f1};
bHi => {arM_aM; arL_aL; brM_bM_x1; brL_bL; freg_f1};
aLo => {arM_aM; arL_aL_x1; brM_bM; brL_bL; freg_f1};
aHi => {arM_aM_x1; arL_aL; brM_bM; brL_bL; freg_f1};
delGamBetAlp => mode _ DragonFP.SetMode[mode, f1];
ENDCASE => Dragon.Assert[FALSE, "Unimplemented load code"] };
[[aluDM, aluDL], aluST0] _ DragonFP.ALU[[arM,arL], [brM,brL], freg, mode];
[[mulDM, mulDL], mulST0] _ DragonFP.MUL[[arM,arL], [brM,brL], freg, mode];
f1 _ f0;
x1 _ x0;
aluCSL1 _ FPCSLdAlu3AB;
mulCSL1 _ FPCSLdMult3AB;
load1 _ load0
};
IF PhB THEN {
IF aluCSU2=unload THEN {
EPData _ Dragon.LTD[aluZ];
EPFaultB _ aluST1;
IF log # IO.noWhereStream THEN {
log.PutF["\n%5g", IO.card[ Dragon.LFD[InstrCountAB] ] ];
log.PutF[" FP-Alu:%08x", IO.card[ Dragon.LFD[EPData] ] ];
log.PutF[" Status:%01x", IO.card[ LOOPHOLE[aluST1, CARDINAL] ] ] } };
IF mulCSU2=unload THEN {
EPData _ Dragon.LTD[mulZ];
EPFaultB _ mulST1;
IF log # IO.noWhereStream THEN {
log.PutF["\n%5g", IO.card[ Dragon.LFD[InstrCountAB] ] ];
log.PutF[" FP-Mul:%08x", IO.card[ Dragon.LFD[EPData] ] ];
log.PutF[" Status:%01x", IO.card[ LOOPHOLE[mulST1, CARDINAL] ] ] } };
};
ENDCELLTYPE;
FP: LAMBDA [logRef: |REF IO.STREAM|] RETURN CELLTYPE AutoName
PORTS [
FPCSLdAlu3AB < EnumType["DragonFP.CSLoad"],
FPCSLdMult3AB < EnumType["DragonFP.CSLoad"],
FPCSUnAlu2AB < EnumType["DragonFP.CSUnload"],
FPCSUnMult2AB < EnumType["DragonFP.CSUnload"],
EPFaultB > EnumType["Dragon.PBusFaults"],
EPData = INT[32], -- X in during A, Z out during B
KBus = INT[32], -- F, L, U in during A
PhA, PhB < BOOL,
InstrCountAB < INT[32] -- For log
]
Expand
fpAlu: FPDevice[type: |Alu|][
CSLd3AB: FPCSLdAlu3AB,
CSUn2AB: FPCSUnAlu2AB];
fpMul: FPDevice[type: |Mul|][
CSLd3AB: FPCSLdMult3AB,
CSUn2AB: FPCSUnMult2AB]
ENDCELLTYPE;
CEDAR
log: IO.STREAM _ IO.noWhereStream;
clocked: BOOL _ FALSE;
�����FP.rose
Copyright c 1984 by Xerox Corporation. All rights reserved.
This module represents the two Weitek Floating Point devices WTL 1164 Multiplier and WTL 1165 ALU. The CSL, L, F, X, Z, S and U pins are bused together. Only the CSU pins are separated. Thus both devices operate in parallel but only one of their outputs can drive the FPStatus and PBus lines.
The F,L and U lines are connected to the Kbus and are valid by the end of PhA (Ka). During the Phase A's with active load and unload chip selects, the K bus is driven by the IFU.
The IFP section of the IFU manages the mask, flag, and mode registers and also generates Reject and FPFault.
The TEN lines are tied to PhB' (this results in the PBus being driven during PhB iff one-cycle-delayed-FPCSUAlu=unload or one-cycle-delayed-FPCSUMult=unload)
Last edited by: Curry February 1, 1985 5:05:27 pm PST
The following assumes that the D regs can be made transparent - Check this
It may be that load nop's may be required between the load and unloads in order to make sure that D gets clocked. The timing is such that the nop load must occur one cycle before the unload which means that it must occur two cycles before the unload in the microcode stream since unloads are driven by IPipe one cycle before loads.
TEN is tied to phB'
Initializer
IF initData#NIL THEN
WITH initData SELECT FROM
pl: Atom.PropList =>
BEGIN
r: REF;
IF (r _ pl.GetPropFromList[$LogRef]) # NIL THEN
fpLogRef _ NARROW[r, REF REF];
END;
ENDCASE => NULL;
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