Directory Rope, DragOpsCross, LizardRosemary;
TranslationNeeds Dragon;
Imports Atom, Basics, ClusterParams, DragonRosemary, DragonRoseExtras, IO, BitOps, RoseEvents, RoseRun, RoseTypes, RoseVectors, DragOpsCrossUtils, ViewerIO;

Cedar
fieldAdr:		INTEGER = DragOpsCross.ProcessorRegister[euField].ORD;
marAdr:		INTEGER = DragOpsCross.ProcessorRegister[euMAR].ORD;

Remark: PROC [ message: Rope.ROPE ] = {RoseRun.DisableableStop[Remark, message]};

FieldOp: PROC[aluLeft, aluRight, fieldDesc: Dragon.HexWord]
RETURNS [result:Dragon.HexWord] =
BEGIN OPEN DragOpsCross, DragOpsCrossUtils;
fd:	FieldDescriptor = CardToFieldDescriptor[fieldDesc MOD 65536];
Left: Word = CardToWord[aluLeft];
Right: Word = CardToWord[aluRight];
out: Word;
shifter: Word = DoubleWordShiftLeft[Left, Right, fd.shift];
mask: Word _ SingleWordShiftRight[OnesWord, 32-fd.mask];
IF fd.insert THEN mask _ DragAnd[mask, SingleWordShiftLeft[OnesWord, fd.shift]];
out _ DragAnd[mask, shifter];
IF fd.insert THEN out _ DragOr[out, DragAnd[DragNot[mask], Right]];
result _ WordToCard[out];
END;

DoubleADD: PROC[al, bl: Dragon.HexWord, carry: BOOL]
RETURNS [sl: Dragon.HexWord, c32: BOOL] = {
Xor: PROC[x, y: BOOL] RETURNS [z: BOOL] = 
{RETURN[(x AND NOT y) OR (y AND NOT x)]};
ai, bi: BOOL;
s: BOOL _ FALSE;
c: BOOL _ carry;
i: INTEGER;
sum: BitOps.BitDWord _ [0,0];
FOR i IN  [1..32]
DO
ai _ EBFL[al, 32-i];
bi _ EBFL[bl, 32-i];
s _ Xor[ai, Xor[bi, c]];
c _ (ai AND bi) OR (bi AND c) OR (ai AND c);
sum _ BitOps.IBID[s,  sum, 32, 32-i];
ENDLOOP;
RETURN[DragonRoseExtras.LFD[sum], c]};

DoubleNOT: PROC[a: Dragon.HexWord] RETURNS [c: Dragon.HexWord] = {
c _ LOOPHOLE[Basics.DoubleNot[LOOPHOLE[a]]]
};

WordOp: PROC[op:{or, and, xor}, left, right:Dragon.HexWord _ 0]
RETURNS[result:Dragon.HexWord] = {
RETURN[DragonRoseExtras.LFD[SELECT op FROM
or				=> BitOps.DOR	[DragonRoseExtras.LTD[left], DragonRoseExtras.LTD[right]],
and			=> BitOps.DAND	[DragonRoseExtras.LTD[left], DragonRoseExtras.LTD[right]],
xor			=> BitOps.DXOR	[DragonRoseExtras.LTD[left], DragonRoseExtras.LTD[right]],
ENDCASE	=> ERROR]] };

ELispFL: PROC[word: Dragon.HexWord] RETURNS[[0..7]] = {
RETURN[ BitOps.ECFD[DragonRoseExtras.LTD[word], 32, 0, 3]] };

EBFL: PROC[word: Dragon.HexWord, index: CARDINAL] RETURNS[BOOL] = {
RETURN[ BitOps.EBFD[DragonRoseExtras.LTD[word], 32, index]] };

DblShiftRt: PROC[msb: BOOL, ltIn, rtIn: Dragon.HexWord]
RETURNS[ltOut, rtOut: Dragon.HexWord] = 
{rtOut _ ShiftRt[EBFL[ltIn, 31], rtIn]; ltOut _ ShiftRt[msb, ltIn]};
ShiftRt: PROC[msb: BOOL, w: Dragon.HexWord] RETURNS[r: Dragon.HexWord] = 
{r_DragonRoseExtras.LFD[BitOps.IBID[msb, BitOps.MDTD[DragonRoseExtras.LTD[w],32,0,31,[0,0],32,1,31],32,0]]};

DblShiftLt: PROC[ltIn, rtIn: Dragon.HexWord, lsb: BOOL]
RETURNS[cry: BOOL, ltOut, rtOut: Dragon.HexWord] =
{cry _ EBFL[ltIn,0]; ltOut _ ShiftLt[ltIn, EBFL[rtIn, 0]]; rtOut _ ShiftLt[rtIn, lsb]};
ShiftLt: PROC[w: Dragon.HexWord, lsb: BOOL] RETURNS[r: Dragon.HexWord] =
{r_DragonRoseExtras.LFD[BitOps.IBID[lsb, BitOps.MDTD[DragonRoseExtras.LTD[w],32,1,31,[0,0],32,0,31],32,31]]};

vectorStream: IO.STREAM _ NIL;

SeeSettle: PROC [event: ATOM, watched, watcherData, arg: REF ANY] --RoseEvents.NotifyProc-- = {
cell: RoseTypes.Cell = NARROW[watcherData];
IF ClusterParams.clusterPanel.enaEULog THEN {
IF vectorStream = NIL THEN {
vectorStream _ ViewerIO.CreateViewerStreams["EU Vectors"].out;
RoseVectors.WriteHeader[vectorStream, cell];
};
RoseVectors.WriteVector[vectorStream, cell];
}
};
;


CELLTYPE "EUCompute"
PORTS [
DPData=INT[32], -- address/data to cache/FP during PhA, data to/from cache/FP during PhB
DPRejectB<BOOL, -- received during PhB

PhA, PhB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL,


KBus= INT[32],
EUSt3AisCBus2BA	< BOOL, -- multiplexor control to store3AB
EURes3BisPBus3AB	< BOOL, -- multiplexor control to cBusResult3BA
EUWriteToPBus3AB < BOOL, -- Tells EU to drive PBus on 3B. Used for Store instructions, and issued every instruction following a DPrejectB. 
EUAluOp2AB		< EnumType["Dragon.ALUOps"], 
EUCondSel2AB		< EnumType["Dragon.CondSelects"],
EUCondition2B	> BOOL,
DShiftAB		< BOOL, -- shift the shift register by 1 bit if ~DNSelectAB
DExecuteAB	< BOOL, -- interpret the content of the shift register if ~DNSelectAB
DNSelectAB	< BOOL, -- if high, hold but don't Execute or Shift
DHoldAB		< BOOL, -- must be high before testing
DDataInAB	< BOOL, -- sampled 1 full cycle after a PhB that DShiftAB is Asserted 
DDataOutAB	= BOOL,  -- changes   in   PhA after a PhB that DShiftAB is Asserted

CBusResult3BA	> INT[32],
ALULeft2AB		> INT[32],
ALURight2AB	> INT[32],
Store2AB			> INT[32]
]

Initializer
RoseEvents.AddWatcher[
event: $Settled,
watcher: [SeeSettle, cell],
watched: cell.sim];
State
aluLeft, aluRight, aluOut: Dragon.HexWord,
result2BA, result3AB, cBusResult3BA: Dragon.HexWord,
store2AB, store2BA, store3AB: Dragon.HexWord,
aAdr, bAdr, cAdr: Dragon.HexByte,
cIsField: BOOL,
EUAluLeftSrc1BA: Dragon.ALULeftSources,
EUAluRightSrc1BA:	Dragon.ALURightSources,
EUStore2ASrc1BA: Dragon.Store2ASources,

ram: ARRAY Dragon.HexByte OF Dragon.HexWord,
field: Dragon.HexWord, -- a copy is kept as RAM[fieldAdr], another copy is in the field unit. Any write is performed to both physical locations, any read is from the most convenient location.
carryAB, carryBA: BOOL, -- carryBA is the output of the adder modified by the opcode of the previous operation and latched if no trap; carryAB is a copy of carryBA if there is no reject or trap.
conditionB: BOOL,

rejectBA: BOOL -- a copy of DPRejectB stable during PhiA

EvalSimple

drive[DPData] _ ignore;
drive[KBus]   _ ignore;

IF PhA THEN {
cReg: DragOpsCross.ProcessorRegister;
DragonRosemary.Assert[aAdr>=0 AND aAdr<164];

IF NOT (rejectBA OR EUCondition2B) THEN {carryAB _ carryBA};
IF NOT rejectBA THEN {
SELECT EUAluLeftSrc1BA FROM
aBus		=> aluLeft _ (SELECT aAdr FROM
DragOpsCross.ProcessorRegister[euConstant].ORD => 0,
ENDCASE => ram[aAdr] -- watch out for illegal addresses
);
rBus		=> aluLeft _  result2BA;
cBus		=> aluLeft _  cBusResult3BA;
ENDCASE	=> DragonRosemary.Assert[FALSE];
SELECT EUAluRightSrc1BA FROM
bBus		=> aluRight _ (SELECT bAdr FROM
DragOpsCross.ProcessorRegister[euConstant].ORD => 0,
ENDCASE => ram[bAdr] -- watch out for illegal addresses
);
rBus		=> aluRight _  result2BA;
cBus		=> aluRight _  cBusResult3BA;
kBus		=> aluRight _  DragonRoseExtras.LFD[KBus];
fCtlReg	=> aluRight _  field;
ENDCASE	=> DragonRosemary.Assert[FALSE];
SELECT EUStore2ASrc1BA FROM
bBus		=> store2AB _ (SELECT bAdr FROM
DragOpsCross.ProcessorRegister[euConstant].ORD => 0,
ENDCASE => ram[bAdr] -- watch out for illegal addresses
);
cBus		=> store2AB _ cBusResult3BA;
rBus		=> store2AB _ result2BA;
ENDCASE	=> DragonRosemary.Assert[FALSE];
result3AB _ result2BA;
drive[DPData] _ drive;
DPData _ DragonRoseExtras.LTD[result2BA];
store3AB _ SELECT EUSt3AisCBus2BA FROM
TRUE		=> cBusResult3BA,
ENDCASE	=> store2BA;
 
IF NOT rejectBA AND cIsField THEN field _ cBusResult3BA;

ALULeft2AB _ DragonRoseExtras.LTD[aluLeft];
ALURight2AB _ DragonRoseExtras.LTD[aluRight];
Store2AB _ DragonRoseExtras.LTD[store2AB];
};

SELECT (cReg _ VAL[cAdr]) FROM
IN [euStack .. euJunk), euMAR, IN [euField .. euBogus) =>
ram[cAdr] _ cBusResult3BA;
euJunk => NULL;
euToKBus => {				-- don't mind reject???
drive[KBus] _ drive;
KBus _ DragonRoseExtras.LTD[cBusResult3BA];
};
ENDCASE => DragonRosemary.Assert[FALSE, "EU cAdr out of range"];

};

IF PhB THEN {
c32, cx: BOOL;

rejectBA _ DPRejectB;

aAdr _ BitOps.ECFD[KBus, 32, Dragon.aRegKBusPos, 8];
bAdr _ BitOps.ECFD[KBus, 32, Dragon.bRegKBusPos, 8];
cAdr _ IF rejectBA THEN DragOpsCross.ProcessorRegister[euMAR].ORD 
ELSE BitOps.ECFD[KBus, 32, Dragon.cRegKBusPos, 8];
cIsField _ BitOps.EBFD[KBus, 32, 24];
EUAluLeftSrc1BA _ VAL[BitOps.ECFD[KBus, 32, 25, 2]];
EUAluRightSrc1BA _ VAL[BitOps.ECFD[KBus, 32, 27, 3]];
EUStore2ASrc1BA _ VAL[BitOps.ECFD[KBus, 32, 30, 2]];

DragonRosemary.Assert[NOT (EUWriteToPBus3AB AND EURes3BisPBus3AB)];
SELECT TRUE FROM
EUWriteToPBus3AB => { -- store in progress
drive[DPData] _ drive;
DPData			_ DragonRoseExtras.LTD[store3AB]; -- send data to Cache (Store)
cBusResult3BA	_ result3AB};
ENDCASE => { -- either a fetch, an op, or a move in progress
IF rejectBA -- Fetch with reject => save address in cBusResult3BA and don't listen to IFU
THEN cBusResult3BA _ result3AB 
ELSE -- Fetch without reject -- IF EURes3BisPBus3AB
THEN {
cBusResult3BA _ DragonRoseExtras.LFD[DPData];}
ELSE cBusResult3BA _ result3AB}; -- op or move ;

store2BA _ store2AB;

carryBA		_ carryAB;
SELECT EUAluOp2AB FROM
SAdd => {
[aluOut, c32] _ DoubleADD[aluLeft, aluRight, carryAB];
result2BA	_ aluOut;
carryBA	_ FALSE};
SSub => {
[aluOut, cx] _ DoubleADD[aluLeft, DoubleNOT[aluRight], NOT carryAB];
c32 _ NOT cx;
result2BA	_ aluOut;
carryBA	_ FALSE};
UAdd => {
[aluOut, c32] _ DoubleADD[aluLeft, aluRight, carryAB];
result2BA	_ aluOut;
carryBA	_ c32};
USub => {
[aluOut, cx] _ DoubleADD[aluLeft, DoubleNOT[aluRight], NOT carryAB];
c32 _ NOT cx;
result2BA	_ aluOut;
carryBA	_ c32};
VAdd, VAdd2 => {
[aluOut, c32] _ DoubleADD[aluLeft, aluRight, FALSE];
result2BA	_ aluOut};
VSub => {
[aluOut, cx] _ DoubleADD[aluLeft, DoubleNOT[aluRight], TRUE];
c32 _ NOT cx;
result2BA	_ aluOut};
LAdd => {
[aluOut, c32] _ DoubleADD[aluLeft, aluRight, FALSE];
result2BA	_ aluOut;
carryBA	_ FALSE};
LSub => {
[aluOut, cx] _ DoubleADD[aluLeft, DoubleNOT[aluRight], TRUE];
c32 _ NOT cx;
result2BA	_ aluOut;
carryBA	_ FALSE};
FOP => {
result2BA _ aluOut _ FieldOp[aluLeft, store2AB, aluRight]};
And => {
result2BA _ aluOut _ WordOp[and, aluLeft, aluRight]};
Or => {
result2BA _ aluOut _ WordOp[or, aluLeft, aluRight]};
Xor => {
result2BA _ aluOut _ WordOp[xor, aluLeft, aluRight]};
BndChk => {
[aluOut, cx] _ DoubleADD[aluLeft, DoubleNOT[aluRight], TRUE];
c32 _ NOT cx;
result2BA	_ aluLeft};
ENDCASE => ERROR Stop["Invalid ALU Operation"];


conditionB _ SELECT EUCondSel2AB FROM
False		=> FALSE,
EZ			=> aluOut=0, -- aluOut=0
LZ			=> (c32 # (EBFL[aluLeft, 0] # EBFL[aluRight, 0])), -- VSub<0
LE			=> (aluOut=0) OR (c32 # (EBFL[aluLeft, 0] # EBFL[aluRight, 0])), -- VSub<=0,
AddressCheckFault	=> aluOut < DragOpsCross.KernalLimit,
NE		=> aluOut#0, -- aluOut#0
GE			=> NOT (c32 # (EBFL[aluLeft, 0] # EBFL[aluRight, 0])), -- VSub>=0
GZ			=> NOT ((aluOut=0) OR (c32 # (EBFL[aluLeft, 0] # EBFL[aluRight, 0]))), -- VSub>0
OvFl		=> ((c32 # EBFL[aluOut, 0]) # (EBFL[aluLeft, 0] # EBFL[aluRight, 0])),
BC			=>  NOT c32,
IL			=>	(ELispFL[aluLeft] IN (0..7) ) OR
				(ELispFL[aluRight] IN (0..7) ) OR
				(ELispFL[aluOut] IN (0..7) ),
NotBC		=> c32,
NotIL		=> NOT ((ELispFL[aluLeft] IN (0..7) ) OR
				(ELispFL[aluRight] IN (0..7) ) OR
				(ELispFL[aluOut] IN (0..7) )),
ModeFault => TRUE,
ENDCASE	=> ERROR Stop["Invalid EUCondition2B Code"];
EUCondition2B _ conditionB;

CBusResult3BA _ DragonRoseExtras.LTD[cBusResult3BA];
};
ENDCELLTYPE;

EULogger: LAMBDA [logRef: |REF IO.STREAM|] RETURN CELLTYPE AutoName
PORTS [
KBus				< INT[32],
ALULeft2AB		< INT[32],
ALURight2AB	< INT[32],
Store2AB			< INT[32],
CBusResult3BA	< INT[32],
DPRejectB		< BOOL,
ResetAB			< BOOL,
PhA, PhB		< BOOL
]

State
phALast: BOOL,
cAdr3BA: DragOpsCross.ProcessorRegister

EvalSimple

IF ResetAB THEN Atom.PutProp[$Cluster, $RegStores, NIL];

IF PhA AND NOT phALast THEN {
phALast _ TRUE;
SELECT cAdr3BA FROM
euJunk, euBogus => NULL;
ENDCASE => Atom.PutProp[$Cluster, $RegStores,
CONS[
NEW[LizardRosemary.RegStoreRec _ [
instr: ClusterParams.clusterPanel.instrCount,
reg: cAdr3BA,
data: DragonRoseExtras.LFD[CBusResult3BA]]],
NARROW[Atom.GetProp[$Cluster, $RegStores], LIST OF REF ANY]]];
};

IF PhB THEN {
phALast _ FALSE;
cAdr3BA _ IF DPRejectB THEN euBogus ELSE VAL[BitOps.ECFD[KBus, 32, Dragon.cRegKBusPos, 8]];
};

ENDCELLTYPE;


EU: LAMBDA [logRef: |REF IO.STREAM|] RETURN CELLTYPE AutoName
PORTS [
DPData=INT[32], -- address/data to cache/FP during PhA, data to/from cache/FP during PhB
DPRejectB<BOOL, -- received during PhB

PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL,


KBus= INT[32],
EUSt3AisCBus2BA	< BOOL, -- multiplexor control to store3AB
EURes3BisPBus3AB	< BOOL, -- multiplexor control to cBusResult3BA
EUWriteToPBus3AB < BOOL, -- Tells EU to drive PBus on 3B. Used for Store instructions, and issued every instruction following an DPrejectB. This is not necessary, but so far OK and simple.
EUAluOp2AB		< EnumType["Dragon.ALUOps"], 
EUCondSel2AB		< EnumType["Dragon.CondSelects"],
EUCondition2B	> BOOL, -- latched to hide precharge in the carry propagator etc
DShiftAB		< BOOL, -- shift the shift register by 1 bit if ~DNSelectAB
DExecuteAB	< BOOL, -- interpret the content of the shift register if ~DNSelectAB
DNSelectAB	< BOOL, -- if high, hold but don't Execute or Shift
DHoldAB		< BOOL, -- must be high before testing
DDataInAB	< BOOL, -- sampled 1 full cycle after a PhB that DShiftAB is Asserted 
DDataOutAB	= BOOL  -- changes   in   PhA after a PhB that DShiftAB is Asserted

]

Expand

ALULeft2AB		: INT[32];
ALURight2AB	: INT[32];
Store2AB			: INT[32];
CBusResult3BA	: INT[32];

compute: EUCompute[];
logger: EULogger[logRef: logRef][]


ENDCELLTYPE

EU.rose
Copyright c 1984 by Xerox Corporation.  All rights reserved.
Last edited by: Monier, May 10, 1984 7:23:23 pm PDT
Last edited by: McCreight, March 11, 1986 12:22:37 pm PST 
Last edited by: Curry, September 5, 1985 11:21:43 pm PDT
Last edited by: Herrmann, September 5, 1985 2:50:49 pm PDT
Louis Monier January 28, 1986 12:22:46 pm PST

??? shows something that has to be discussed and fixed
From here on, the code is copied from LizardHeartImpl, which in turn purports to be identical to the manual.
The shifter output has the input double word shifted left by fd.shift bits
The default mask has fd.mask 1s right-justified in the word
fd.insert => clear rightmost fd.shift bits of the mask 
1 bits in the mask select the shifter output
fd.backR => 0 bits in the mask select bits from Right to OR in to the result
Returns a+b+carry and c32, where a and b are considered to be signed numbers

Signal names obey the following convention:  If a signal x is computed during PhA and remains valid throughout the following PhB, it is denoted as xAB.  If x is computed during PhA and can change during the following PhB (as, for example, in precharged logic), it is denoted as xA.  In this latter case, a client wanting to use x during PhB must receive it in his own latch open during PhA.  xBA and xB are defined symmetrically.  Positive logic is assumed (dragon.Asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., DPNPErrorB for PBus Negative-TRUE Parity Error).

P Interface
Timing and housekeeping interface
ResetAB<BOOL,	-- not needed by the EU
I interface
PhiB: a, b, and c ram addresses are multiplexed on KBus.  a=[0..7], b=[8..15], c=[16..23], cIsField=[24], EUAluLeftSrc1BA=[25..26], EUAluRightSrc1BA=[27..29], EUStore2ASrc1BA=[30..31].
PhiA: data moves from EU -> IFU iff cAdr = euToKBus during the previous PhiB, otherwise IFU may be using bus to pass data to EU or control to FP.

The following signals change during 1B and are stable during 2A.
EUAluLeftSrc1BA	< EnumType["Dragon.ALULeftSources"],
EUAluRightSrc1BA	< EnumType["Dragon.ALURightSources"],
EUStore2ASrc1BA	< EnumType["Dragon.Store2ASources"],

Serial debugging interface
All the following signals change during PhA and PhB, giving an entire clock cycle for them to change, are sampled during PhB, and are applied to the data path during the following PhA. All signals are not used !!! JH
Extra signals to the logger

Pipeline registers

RAM, RAM addresses and various aliased registers
The RAM is organised as follows (Ref DragOpsCross):
registers 0 through 127 constitute the stack
128: euJunk i.e. no write
129: euToKBus, write result to KBus
130: euMAR
131: euField
132 through 143 are constants registers
144 through 159 are auxilliary registers
Any aAdr larger than 160 is illegal


Bits and pieces for the ALU and the Field Unit
Other pieces from the Control pipeline
PhiA phase. Note that rejectBA alone inhibits almost any state change during PhiA

No simultaneous bypass control signals on



Always send address to Cache during PhiA
-- On every PhA with RejectBA the faulty address is saved in ram[euMAR]; the EU generates the appropriate cAdr when RejectBA is sensed, so the rule is: we always write into the register file! (Q: what about euToKBus? LMM)



PhiB phase. Most of the computations take place during PhiB
DPRejectB is valid at the end of PhiB but bogus during PhiA, so it must be latched at the end of PhiB. A current problem is that the source for cBusResult3BA depends upon DPRejectB, and the choice is made during the same PhiB as it is received. So this statement has to be first.
Updating the RAM addresses
PBus: notice that in case of reject during a store, we keep sending the data even though it is useless
save the address in cBusResult3BA, done normally since NOT EURes3BisPBus3AB;
Data pipe
Alu and Field Unit computation
Set Default values of state
Condition and trap generation

P Interface
DPFaultB<EnumType["Dragon.PBusFaults"], -- received during PhB, together with the last DPRejectB of a sequence. On the next PhA, the EU still freezes, but saves the Fault address in RAM. No instruction following a faulty Cache access should modify the carry!
Timing and housekeeping interface
I interface
PhiB: a, b, and c ram addresses are multiplexed on KBus.  a=[0..7], b=[8..15], c=[16..23], cIsField=[24], EUAluLeftSrc1BA=[25..26], EUAluRightSrc1BA=[27..29], EUStore2ASrc1BA=[30..31].
PhiA: data moves from EU -> IFU iff cAdr in [ifuXBus..ifuLast] during the previous PhiB, otherwise IFU may be using bus to pass data to EU or control to FP.

The following signals change during 1B and are stable during 2A.
EUAluLeftSrc1BA	< EnumType["Dragon.ALULeftSources"],
EUAluRightSrc1BA	< EnumType["Dragon.ALURightSources"],
EUStore2ASrc1BA	< EnumType["Dragon.Store2ASources"],

Serial debugging interface
All the following signals change during PhA and PhB, giving an entire clock cycle for them to change, are sampled during PhB, and are applied to the data path during the following PhA. All signals are not used !!! JH
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