MakeEU:
PW.UserProc =
BEGIN
-- A large via of specified size, with a 10l extension of m2 on the left, m1 on the right
MakeVia:
PROC [x, y:
INT]
RETURNS [via:
PW.ObPtr] =
BEGIN
via ← PW.CreateEmptyCell[];
PW.IncludeInCell[design, via, PWCmos.Rect[CMos.met2, [x-4*l, y]], [0, 0]];
PW.IncludeInCell[design, via, PWCmos.Rect[CMos.met, [x-4*l, y]], [4*l, 0]];
PW.IncludeInCell[design, via, PWCmos.Rect[CMos.cut2, [x-10*l, y-2*l]], [5*l, l]];
PW.IncludeInDirectory[design, via, "via"];
END;
RightExtension:
PROC [design:
CD.Design, obj:
PW.ObPtr, extensionOutOfIR:
INT ← 0]
RETURNS [cell:
PW.ObPtr] =
BEGIN
ProcessPinOnEdge: PWPins.AppEnumerator =
BEGIN
side: PWPins.Side ← PWPins.GetSide[obj, app].side;
IF side=PWPins.right
THEN {
name: ROPE ← CDPinObjects.GetName[app];
SELECT
TRUE
FROM
Rope.Equal[name, "vdd"] =>
-- just a piece of wire
PW.IncludeInCell[design, cell,
PWCmos.Rect[CMos.met2, [bridgeWidth, app.ob.size.y]],
[iRect.x1, app.location.y-iRect.y1]];
Rope.Equal[name, "gnd"] =>
-- a via of appropriate size
PW.IncludeInCell[design, cell,
MakeVia[bridgeWidth, app.ob.size.y],
[iRect.x1, app.location.y-iRect.y1]];
ENDCASE => NULL;
};
END;
bridgeWidth: INT = 14*l;
iRect: CD.Rect ← CD.InterestRect[obj]; -- copy interestRect of obj;
-- Start with an empty cell of appropriate interestRect (origin in 0,0)
cell ← PW.CreateEmptyCell[];
CDCells.SetInterestRect[cell, [0, 0, bridgeWidth, iRect.y2-iRect.y1]]; -- set interestRect of cell
-- Parse the pins and make the bridge -> vdd in m2, gnd in m1
[] ← PWPins.EnumerateEdgePins[obj, ProcessPinOnEdge];
PW.IncludeInCell[design,
cell,
PWCmos.Rect[CMos.met2, [extensionOutOfIR, iRect.y2-iRect.y1]], -- hack
[bridgeWidth, 0]];
PW.IncludeInCell[design,
cell,
PWCmos.Rect[CMos.met, [extensionOutOfIR, iRect.y2-iRect.y1]], -- hack
[bridgeWidth, 0]];
PW.IncludeInDirectory[design, cell, "rightExtension"];
END;
EUIncreasingGen:
PROC
RETURNS [eu:
PW.ObPtr] =
BEGIN
rightPowerBus: PW.ObPtr;
-- Assemble the datapath and control
eu ←
PW.AbutListY[design,
LIST[
EuGen.ResultRegsGen[design],
EuGen.ALUGen[design],
EuGen.FieldUnitGen[design],
EuGen.PipeLineRegsGen[design],
EuGen.FDRegsGen[design],
EuGen.AdrRegGen[design],
EuGen.DrivekBusGen[design],
EuGen.BitLinesReadWriteGen[design],
EuGen.BitLinesMuxesGen[design],
EuGen.RAMGen[design]
]];
-- Add the power bus on the right
rightPowerBus ← RightExtension[design, eu, 200*l];
eu ← PW.AbutX[design, eu, rightPowerBus];
PW.RenameObject[design, eu, "EU"];
END;
RenamePadsProc: PWPins.RenameProc =
BEGIN
newRope ←
SELECT
TRUE
FROM
Rope.Match["*.dataIn", oldRope] => Rope.Substr[oldRope, 0, Rope.Size[oldRope]-7],
Rope.Match["*.dataOut", oldRope] => Rope.Substr[oldRope, 0, Rope.Size[oldRope]-8],
ENDCASE => oldRope;
END;
PadFrame:
PROC
RETURNS [frame:
PW.ObPtr] =
BEGIN
padDescr: PWDescr.Descriptor;
-- Specify the types of the items composing the pad frame descriptor
padDescr ← PWDescr.RopesToDescr[padNames];
PWDescr.SetTypePad[padDescr, "PhA", PGA144.Single[3], $Clock];
PWDescr.SetTypePad[padDescr, "nPhA", PGA144.Single[4], $Clock];
PWDescr.SetTypePad[padDescr, "PhB", PGA144.Single[5], $Clock];
PWDescr.SetTypePad[padDescr, "nPhB", PGA144.Single[6], $Clock];
PWDescr.SetTypePad[padDescr, "EUAluOp2AB", PGA144.Segment[7,5], $In];
PWDescr.SetTypePad[padDescr, "EULoadField3BA", PGA144.Single[12], $In];
PWDescr.SetTypePad[padDescr, "nrejectBA", PGA144.Single[13], $In];
PWDescr.SetTypePad[padDescr, "nhold2BA", PGA144.Single[14], $In];
PWDescr.SetTypePad[padDescr, "EURes3BisPBus3AB", PGA144.Single[15], $In];
PWDescr.SetTypePad[padDescr, "EUWriteToPBus3AB", PGA144.Single[16], $In];
PWDescr.SetTypePad[padDescr, "DExecute", PGA144.Single[17], $In];
PWDescr.SetTypePad[padDescr, "DStateAddress", PGA144.Segment[20,4], $In];
PWDescr.SetTypePad[padDescr, "EPData.enableWrite", PGA144.Single[38], $In];
PWDescr.SetTypePad[padDescr, "EPData", PGA144.Segment[39,32], $IOTst];
PWDescr.SetTypePad[padDescr, "empty19", PGA144.Segment[87,19],$Empty];
PWDescr.SetTypePad[padDescr, "kBus", PGA144.Segment[110,32],$IOTst];
PWDescr.SetTypePad[padDescr, "kBus.enableWrite", PGA144.Single[144], $In];
-- This generates a standard pad frame; Pradeep will use the same one, so that we can share probe cards
frame ← PGA144.MakePadFrame[design, padDescr, padFrameInnerSize];
END;
MakeLogo:
PROC
RETURNS [logo:
PW.ObPtr] =
BEGIN
now, name: ROPE;
font: Graphics.FontRef;
now ← Convert.RopeFromTime[from: BasicTime.Now[], start: years, end: days];
font ← Graphics.MakeFont["TimesRomanD24"];
logo ← CDCreateLabels.CreateTextCell[design, name, font, 4, CMos.met];
END;
-- Prepares the inside of the EU for routing by Onion
RenameInnerPins:
PROC [design:
CD.Design, obj:
PW.ObPtr]
RETURNS [cell:
PW.ObPtr] =
BEGIN
Rename: PWPins.RenameProc=
BEGIN
Propagate:
PROC [lNames:
LIST OF ROPE] =
{newRope ← NIL;
FOR l:
LIST
OF
ROPE ← lNames, l.rest
WHILE l#
NIL
DO
IF Rope.Find[oldRope, l.first]#-1 THEN {newRope ← oldRope; EXIT};
ENDLOOP;};
Propagate[padNames];
END;
cell ← PWPins.RenamePins[design, obj, Rename];
END;
MakeCompleteEu:
PROC
RETURNS [eu:
PW.ObPtr] =
BEGIN
inner, outer, copyrightSign, myName: CD.ObPtr;
innerPos: CD.Position;
layersParams: Onion.LayersParameters ← Onion.defaultLayersParameters;
layersParams.wireExtendProc ← Onion.WireExtendPolToMetForPads;
EuControl.InitEUControl[design];
-- Generate the eu
inner ← Onion.MakeInner[design, RenameInnerPins[design, EUIncreasingGen[]]];
-- Generate the logo
PW.SetDefaultSource[design, PW.OpenDesign["///Logo.dale"]];
copyrightSign ← PW.Get[design, "copyrightSign"];
myName ← PW.Get[design, "myName"];
-- Generate the pad frame
outer ← PGA144.MakeOuter[design, PadFrame[], RenamePadsProc];
-- Position the eu, vertically centered, right flushed
innerPos.x ← PW.Size[outer].x-PW.Size[inner].x; -- hack
innerPos.y ← Onion.Center[inner, outer].y;
eu ← Onion.LRSRoute[design, inner, outer, innerPos, layersParams].cell;
-- Include the logo (in the pad frame)
PW.IncludeInCell[design, eu, copyrightSign, [-500*l, 0], 2];
PW.IncludeInCell[design, eu, myName, [PW.Size[eu].x+300*l, 0], 6];
END;
MakeQuickCompleteEu: PROC RETURNS [eu: PW.ObPtr] =
BEGIN
inner, outer: CD.ObPtr;
innerPos: CD.Position;
layersParams: Onion.LayersParameters ← Onion.defaultLayersParameters;
layersParams.wireExtendProc ← Onion.WireExtendPolToMetForPads;
PW.SetDefaultSource[design, NIL];
inner ← Onion.MakeInner[design, RenameInnerPins[design, PW.Get[design, "eu"]]];
outer ← PGA144.MakeOuter[design, PadFrame[], RenamePadsProc];
-- Position the eu, vertically centered, right flushed
innerPos.x ← PW.Size[outer].x-PW.Size[inner].x; -- hack
innerPos.y ← Onion.Center[inner, outer].y;
eu ← Onion.LRSRoute[design, inner, outer, innerPos, layersParams].cell;
-- Include the logo!!! (maybe in the pad frame)
END;
EuControl.InitEUControl[design];
RETURN[PadFrame[]];
RETURN[PGA144.MakeOuter[design, PadFrame[], RenamePadsProc]];
RETURN[EUIncreasingGen[]];
RETURN[MakeCompleteEu[]];
RETURN[MakeQuickCompleteEu[]];
RETURN[EuGen.RAMGen[design]];
RETURN[EuGen.BitLinesMuxesGen[design]];
RETURN[EuGen.BitLinesReadWriteGen[design]];
RETURN[EuGen.DrivekBusGen[design]];
RETURN[EuGen.AdrRegGen[design]];
RETURN[EuGen.FDRegsGen[design]];
RETURN[EuGen.PipeLineRegsGen[design]];
RETURN[EuGen.FieldUnitGen[design]];
RETURN[EuGen.ALUGen[design]];
RETURN[EuGen.ResultRegsGen[design]];
END;