Directory Rope, DragOpsCross; Imports EUOps, Dragon, RoseTypes, BitOps; Open EUOps; EUKport: CELL [ KBus = INT[32], cBus < INT[32], ConstBus > INT[32], aAddBus, bAddBus, cAddBus > INT[8], -- sent during PhB rejectBA < BOOL, PhA, PhB EU IF WriteToIFUBA THEN KBus _ cBus ELSE ConstBus _ KBus; }; IF PhB THEN { -- get a,b,c addresses from IFU, and hold them (dynamically???) aAddBus _ BitOps.ECFD[KBus, 32, 0, 8]; bAddBus _ BitOps.ECFD[KBus, 32, 8, 8]; cAddBus _ BitOps.ECFD[KBus, 32, 16, 8]; WriteToIFUBA _ cAddBus >= 240 -- real test is: cAddBus IN [ifuXBus .. ifuLast]; easily detected as cAddBus=1111xxxxB. }; ENDCELL; EUPport: CELL [ EPData=INT[32], EPRejectB BOOL, -- a copy of EPRejectB stable during PhiA cBus > INT[32], rBus < INT[32], storeBus < INT[32], parityStore < BOOL, EURes3AgetscBusB < BOOL, -- on 2B EURes3BgetsPB < BOOL, -- on 3B EUWriteToPBusAB < BOOL, -- sent by the IFU during 3A EUCheckPParityAB < BOOL, -- sent by the IFU during 3A PhA, PhB Cache rejectBA _ EPRejectB; Dragon.Assert[NOT (EUWriteToPBusAB AND EURes3BgetsPB)]; -- if write, no read SELECT TRUE FROM -- store or floating-point operation in progress (reject does not matter) EUWriteToPBusAB => { EPData _ storeBus; -- send data to Cache (Store) EPParityB _ parityStore; -- send parity to Cache result3B _ result3A}; -- save the address in result3B -- successful fetch (NOT EUWriteToPBusAB) AND EURes3BgetsPB AND (NOT rejectBA) => { result3B _ LFD[EPData]; parityResult3B _ EPParityB; IF parityResult3B AND EUCheckPParityAB THEN EPNPErrorB _ TRUE }; -- and then we don't want to know -- fetch with reject => save address in result3B and don't listen to IFU (NOT EUWriteToPBusAB) AND EURes3BgetsPB AND (rejectBA) => result3B _ result3A; -- op or move (NOT EUWriteToPBusAB) AND (NOT EURes3BgetsPB) AND (NOT rejectBA) => result3B _ result3A; -- this should not happen if the IFU is OK ENDCASE => ERROR; }; ENDCELL vEUPorts.rose Last edited by: Monier, October 2, 1984 6:47:01 pm PDT IFU <-> Kport Data to and from EU, addresses to RAM Reject Timing and housekeeping interface EU <-> PBus Output Address Path Data Path Mux selectors Timing and housekeeping interface EPRejectB is valid at the end of PhiB but bogus during PhiA, so it must be latched at the end of PhiB. A current problem is that the source for result3 depends upon EPRejectB, and the choice is made during the same PhiB as it is received. So this statement has to be first. Notice that in case of reject during a store, we keep sending the data even though it is useless ÊߘšÏb ™ Jšœ6™6—J™Jš œ˜Jšœ"˜)Jšœ˜ J™šÐblœÏkœ˜™ JšœŸœ˜—šœ%™%JšœŸœ˜Jšœ Ÿœ˜JšœŸœÏc˜6—™Jšœ Ÿœ˜—šœ!™!Jšœ Ÿœ˜JšœŸœ˜ JšœŸ˜—J˜J˜šž˜JšœŸœŸ˜J˜—š ˜ š ŸœŸœŸœ Ÿœ ˜1JšŸœŸœ ˜ JšŸœ˜J˜J˜—šŸœŸœ ?˜MJšœŸœ˜&JšœŸœ˜&JšœŸœ˜'Jšœ W˜uJ˜———JšŸœ˜J˜šžœŸœ˜™ JšœŸœ˜Jšœ Ÿœ˜Jšœ Ÿœ˜Jšœ Ÿœ˜Jšœ Ÿœ )˜:—šœ™JšœŸœ˜—™ JšœŸœ˜—™ Jšœ Ÿœ˜JšœŸœ˜—šœ ™ JšœŸœ ˜!JšœŸœ ˜JšœŸœ ˜4JšœŸœ ˜5—šœ!™!Jšœ Ÿœ˜JšœŸœ˜ JšœŸ˜J˜—J˜šž˜J˜#JšœŸœ $˜:—J˜š ˜ š ŸœŸœŸœ Ÿœ *˜IJšœ˜J˜J˜—šŸœŸœ ˜#šœ˜Jš ¥œ  c™‘—Jšœ`™`JšœŸœŸœ ˜LJ˜šŸœŸœŸ˜š I˜Išœ˜Jšœ ˜0Jšœ ˜0Jšœ ˜5——š ˜š œŸœŸœŸœŸœ˜?Jšœ Ÿœ ˜Jšœ˜Jš ŸœŸœŸœŸœ !˜b——š H˜HšœŸœŸœŸœ˜:Jšœ˜——š  ˜ š œŸœŸœŸœŸœŸœ ˜CJšœ˜——š *˜*JšŸœŸœ˜——J˜———šŸ˜J˜—J˜—…— R§