EURegs.rose
Last edited by: Monier, October 9, 1984 11:47:05 am PDT
Directory Rope, DragOpsCross;
Imports EUOps, Dragon, RoseTypes, CacheOps, BitOps;
Open EUOps;
EULeftOp:
CELL [
Output
LeftOpBus > INT[32],
Input mux
aBus < INT[32],
rBus < INT[32],
cBus < INT[32],
saveLeftOp < BOOL,
Mux selectors
EULeftOpSrcA < EnumType["Dragon.LeftOpSources"],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
LeftOp: Dragon.HexWord
EvalSimple
IF PhA
AND
NOT rejectBA
AND
NOT saveLeftOp
THEN {
LeftOp ←
SELECT EULeftOpSrcA
FROM
rBus= => LFD[rBus], -- also during a MulStep, responsability of the IFU
cBus => LFD[cBus],
aBus => LFD[aBus], -- watch out for illegal addresses
ENDCASE => ERROR;
LeftOpBus ← LTD[LeftOp];
};
ENDCELL;
EURightOp:
CELL [
Output
RightOpBus > INT[32],
Input mux
bBus < INT[32],
ConstBus < INT[32],
rBus < INT[32],
cBus < INT[32],
Mux selectors
EURightOpSrcA < EnumType["Dragon.RightOpSources"],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
RightOp: Dragon.HexWord
EvalSimple
IF PhA
AND
NOT rejectBA
THEN {
RightOp ←
SELECT EURightOpSrcA
FROM
rBus => LFD[rBus],
cBus => LFD[cBus],
contBus => LFD[ConstBus],
bBus => LFD[bBus],
ENDCASE => ERROR;
RightOpBus ← LTD[RightOp];
};
ENDCELL;
EUResult2B:
CELL [
Input mux
sBus < INT[32],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
result2B: Dragon.HexWord
EvalSimple
IF PhB
THEN {
result2B ← LFD[sBus];
rBus ← LTD[result2B];
};
ENDCELL;
EUStore:
CELL [
Output
storeBus > INT[32],
parityStore > BOOL,
Input mux
bBus < INT[32],
cBus < INT[32], -- used twice for bypass
rBus < INT[32],
Mux selectors
EUStore2ASrcA < EnumType["Dragon.Store2ASources"],
EUStore3AgetscBusB < BOOL,
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
store2A, store2B, store3A: Dragon.HexWord,
parityStore3A: BOOL -- parity associated to the register
EvalSimple
IF PhA
AND
NOT rejectBA
THEN {
store2A ←
SELECT EUStore2ASrcA
FROM
rBus => LFD[rBus],
cBus => LFD[cBus],
bBus => LFD[bBus],
ENDCASE => ERROR;
store3A ← IF EUStore3AgetscBusB THEN LFD[cBus] ELSE store2B;
parityStore3A ← IF EUStore3AgetscBusB THEN CacheOps.Parity32[LFD[cBus]] ELSE CacheOps.Parity32[store2B]; -- the parity generator is after the mux, probably after the latch
storeBus ← LTD[store3A];
parityStore ← parityStore3A;
};
IF PhB
THEN {
Data pipe
store2B ← store2A;
};
ENDCELL