<> <> <<>> Directory Rope, DragOpsCross; Imports EUOps, Dragon, RoseTypes; Open EUOps; <<>> Cedar fieldAdr: INTEGER = PRtoByte[euField]; -- aliased with field in the field unit mqAdr: INTEGER = PRtoByte[euMQ]; marAdr: INTEGER = PRtoByte[euMAR]; -- controlled by the IFU constAdr: INTEGER = PRtoByte[euConstant]; XBusAdr: INTEGER = PRtoByte[ifuXBus]; -- the first IFU register ifuLastAdr: INTEGER = PRtoByte[ifuLast]; -- the last IFU register noMatchAdr: INTEGER = PRtoByte[euJunk]; -- the "no write" register euBogusAdr: INTEGER = PRtoByte[euBogus]; -- [euBogus..euLast] are not legal euLastAdr: INTEGER = PRtoByte[euLast]; ; EURAMReadDec: CELL [ aAddBus, bAddBus < INT[8], SelectALine, SelectBLine > INT[8], -- actually encoded in unary <> PhA, PhB INT[8], -- actually encoded in unary writeFieldBA > BOOL, rejectBA, faultBA < BOOL, <> PhA, PhB> (NOT rejectBA) AND (cAdr IN [0 .. constAdr+12)) => cAdr, <> (NOT rejectBA) AND (cAdr IN [XBusAdr .. ifuLastAdr]) => noMatchAdr, <> rejectBA => noMatchAdr, <> ENDCASE => ERROR Stop["EU cAdr out of range"]; }; IF PhB THEN { -- get the address from K; detect special case of alias (field) cAdr _ cAddBus; Dragon.Assert[NOT (cAdr IN [euBogusAdr..euLastAdr]) ]; writeFieldBA _ (cAdr = fieldAdr); }; ENDCELL; EURAMArray: CELL [ SelectALine, SelectBLine, SelectCLine < INT[8], aBus > INT[32], bBus > INT[32], cBus < INT[32], <> PhA, PhB> ENDCELL; <<>> EURam: CELL [ <> aAddBus, bAddBus, cAddBus < INT[8], -- received during PhB <> aBus > INT[32], bBus > INT[32], cBus < INT[32], rejectBA, faultBA < BOOL, writeFieldBA > BOOL, <> PhA, PhB>