EURam.rose
Last edited by: Monier, September 25, 1984 11:53:44 am PDT
Directory Rope, DragOpsCross;
Imports EUOps, Dragon, RoseTypes;
Open EUOps;
Cedar
fieldAdr: INTEGER = PRtoByte[euField]; -- aliased with field in the field unit
mqAdr: INTEGER = PRtoByte[euMQ];
marAdr: INTEGER = PRtoByte[euMAR]; -- controlled by the IFU
constAdr: INTEGER = PRtoByte[euConstant];
XBusAdr: INTEGER = PRtoByte[ifuXBus]; -- the first IFU register
ifuLastAdr: INTEGER = PRtoByte[ifuLast]; -- the last IFU register
noMatchAdr: INTEGER = PRtoByte[euJunk]; -- the "no write" register
euBogusAdr: INTEGER = PRtoByte[euBogus]; -- [euBogus..euLast] are not legal
euLastAdr: INTEGER = PRtoByte[euLast];
;
EURAMReadDec:
CELL [
aAddBus, bAddBus < INT[8],
SelectALine, SelectBLine > INT[8], -- actually encoded in unary
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
aAdr, bAdr: Dragon.HexByte
EvalSimple
IF PhA
THEN {
-- pulse read lines
SelectALine ← aAdr;
SelectBLine ← bAdr;
};
IF PhB
THEN {
-- get the addresses from K and check if valid read addresses
aAdr ← aAddBus;
Dragon.Assert[aAdr IN [0..constAdr+12)];
bAdr ← bAddBus;
Dragon.Assert[bAdr IN [0..constAdr+12)];
};
ENDCELL;
EURAMWriteDec:
CELL [
cAddBus < INT[8],
SelectCLine > INT[8], -- actually encoded in unary
writeFieldBA > BOOL,
rejectBA, faultBA < BOOL,
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
cAdr: Dragon.HexByte
EvalSimple
IF PhA
THEN {
--
SelectCLine ←
SELECT
TRUE
FROM
The normal write case (we might want to refine the test for nonexisting registers)
(NOT rejectBA) AND (cAdr IN [0 .. constAdr+12)) => cAdr,
We send a value back to the IFU through KBus, so no write in the RAM
(NOT rejectBA) AND (cAdr IN [XBusAdr .. ifuLastAdr]) => noMatchAdr,
The normal reject case: no write at all
rejectBA => noMatchAdr,
The bug
ENDCASE => ERROR Stop["EU cAdr out of range"];
};
IF PhB
THEN {
-- get the address from K; detect special case of alias (field)
cAdr ← cAddBus;
Dragon.Assert[NOT (cAdr IN [euBogusAdr..euLastAdr]) ];
writeFieldBA ← (cAdr = fieldAdr);
};
ENDCELL;
EURAMArray:
CELL [
SelectALine, SelectBLine, SelectCLine < INT[8],
aBus > INT[32],
bBus > INT[32],
cBus < INT[32],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
ram: ARRAY Dragon.HexByte OF Dragon.HexWord -- the RAM is actually laid out as an array [0..84] of double Dragon.HexWord
EvalSimple
IF PhA
THEN {
--
aBus ← LTD[ram[SelectALine]]; -- we always read the RAM.
bBus ← LTD[ram[SelectBLine]];
IF SelectCLine # noMatchAdr THEN ram[SelectCLine] ← LFD[cBus]; -- in the design, we don't have to test since there is no physical location at this address
};
During PhB the RAM Array is precharged
ENDCELL;
EURam:
CELL [
from k-port
aAddBus, bAddBus, cAddBus < INT[8], -- received during PhB
read and write ports
aBus > INT[32],
bBus > INT[32],
cBus < INT[32],
rejectBA, faultBA < BOOL,
writeFieldBA > BOOL,
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
Expand
SelectALine, SelectBLine, SelectCLine : INT[8];
RAMArray: EURAMArray[];
RAMReadDec: EURAMReadDec[];
RAMWriteDec: EURAMWriteDec[]
ENDCELL