EUPorts.rose
Last edited by: Monier, October 2, 1984 6:47:01 pm PDT
Directory Rope, DragOpsCross;
Imports EUOps, Dragon, RoseTypes, BitOps;
Open EUOps;
EUKport: CELL [
IFU <-> Kport
KBus = INT[32],
Data to and from EU, addresses to RAM
cBus < INT[32],
ConstBus > INT[32],
aAddBus, bAddBus, cAddBus > INT[8], -- sent during PhB
Reject
rejectBA < BOOL,
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
WriteToIFUBA: BOOL ← FALSE
EvalSimple
IF PhA AND NOT rejectBA THEN { -- data IFU <-> EU
IF WriteToIFUBA THEN KBus ← cBus
ELSE ConstBus ← KBus;
};
IF PhB THEN { -- get a,b,c addresses from IFU, and hold them (dynamically???)
aAddBus ← BitOps.ECFD[KBus, 32, 0, 8];
bAddBus ← BitOps.ECFD[KBus, 32, 8, 8];
cAddBus ← BitOps.ECFD[KBus, 32, 16, 8];
WriteToIFUBA ← cAddBus >= 240 -- real test is: cAddBus IN [ifuXBus .. ifuLast]; easily detected as cAddBus=1111xxxxB.
};
ENDCELL;
EUPport: CELL [
EU <-> PBus
EPData=INT[32],
EPRejectB<BOOL,
EPParityB=BOOL,
EPNPErrorB=BOOL,
rejectBA > BOOL, -- a copy of EPRejectB stable during PhiA
Output
cBus > INT[32],
Address Path
rBus < INT[32],
Data Path
storeBus < INT[32],
parityStore < BOOL,
Mux selectors
EURes3AgetscBusB < BOOL, -- on 2B
EURes3BgetsPB < BOOL, -- on 3B
EUWriteToPBusAB < BOOL, -- sent by the IFU during 3A
EUCheckPParityAB < BOOL, -- sent by the IFU during 3A
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
result3A, result3B: Dragon.HexWord,
parityResult3B: BOOL -- parity associated to the register
EvalSimple
IF PhA AND NOT rejectBA THEN { --Always send address to Cache during PhiA
EPData ← rBus;
};
IF PhB THEN { -- data: EU <-> Cache
rejectBA ← EPRejectB;
EPRejectB is valid at the end of PhiB but bogus during PhiA, so it must be latched at the end of PhiB. A current problem is that the source for result3 depends upon EPRejectB, and the choice is made during the same PhiB as it is received. So this statement has to be first.
Notice that in case of reject during a store, we keep sending the data even though it is useless
Dragon.Assert[NOT (EUWriteToPBusAB AND EURes3BgetsPB)]; -- if write, no read
SELECT TRUE FROM
-- store or floating-point operation in progress (reject does not matter)
EUWriteToPBusAB => {
EPData ← storeBus; -- send data to Cache (Store)
EPParityB ← parityStore; -- send parity to Cache
result3B ← result3A}; -- save the address in result3B
-- successful fetch
(NOT EUWriteToPBusAB) AND EURes3BgetsPB AND (NOT rejectBA) => {
result3B ← LFD[EPData];
parityResult3B ← EPParityB;
IF parityResult3B AND EUCheckPParityAB THEN EPNPErrorB ← TRUE }; -- and then we don't want to know
-- fetch with reject => save address in result3B and don't listen to IFU
(NOT EUWriteToPBusAB) AND EURes3BgetsPB AND (rejectBA) =>
result3B ← result3A;
-- op or move
(NOT EUWriteToPBusAB) AND (NOT EURes3BgetsPB) AND (NOT rejectBA) =>
result3B ← result3A;
-- this should not happen if the IFU is OK
ENDCASE => ERROR;
};
ENDCELL