EUField.rose
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by: Monier, September 25, 1984 12:06:21 pm PDT
Directory Rope, DragOpsCross;
Imports EUOps, BitOps, DragOpsCrossUtils;
Open EUOps;
Cedar
ShiftLeft2DtoD: PROC[left, right: BitOps.BitDWord, index: CARDINAL] RETURNS[shiftout: BitOps.BitDWord] =
BEGIN
temp: BitOps.BitDWord;
SELECT index FROM
0 => shiftout ← left;
32 => shiftout ← right;
IN [1..32) =>
{temp ← BitOps.MDTD[right, 32, 0, index, temp, 32, 32-index, index];
shiftout ← BitOps.MDTD[left, 32, index, 32-index, temp, 32, 0, 32-index]};
ENDCASE => ERROR;
END;
;
FUFieldDescr: CELL [
Source of field descriptor
cBus < INT[32], -- only for updating field
ConstBus < INT[32], -- only for updating kBusAB
Control
EUAluOpAB < EnumType["Dragon.ALUOps"],
writeFieldBA < BOOL, -- provided by the RAM
Field descriptor fields
insert > BOOL,
fdshift > INT[6], -- actually between 0 and 32
fdmask > INT[6], -- actually between 0 and 32
Timing and housekeeping interface
rejectBA < BOOL,
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
State
field: Dragon.HexWord, -- aliased with RAM[fieldAdr]. Any write is performed in all physical locations under control of writeFieldBA (from the RAM). External read is from the RAM.
kBusAB: Dragon.HexWord -- a temporary latch to hold ConstBus during one phase
EvalSimple
fd: DragOpsCross.FieldDescriptor;
IF PhA AND NOT rejectBA THEN {
IF writeFieldBA THEN field ← LFD[cBus]; --same thing happens in the RAM
kBusAB ← LFD[ConstBus];
};
IF PhB THEN { -- control signals fired during PhB
fd ← DragOpsCrossUtils.CardToFieldDescriptor[(IF EUAluOpAB = FOPK THEN kBusAB ELSE field) MOD 65536];
insert ← fd.insert;
fdshift ← fd.shift;
fdmask ← fd.mask;
};
ENDCELL;
FUMaskGen: CELL [
Width
width < INT[6],
Mask
mask > INT[32],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
EvalSimple
No problem of range: width is properly typed. Tested by interp.
mask ← BitOps.doubleMasks[width]; -- a cloud of zeros followed by "width" ones
ENDCELL;
FUShifter: CELL [
Source of data
LeftOpBus < INT[32],
RightOpBus < INT[32],
Control
fdshift < INT[6],
Shifter output
shiftout > INT[32],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
EvalSimple
IF PhB THEN { -- shift left the double word (OpLeftBus,OpRightBus)
shiftout ← ShiftLeft2DtoD[LeftOpBus, RightOpBus, fdshift];
};
ENDCELL;
FUMerge: CELL [
Sources
mask1 < INT[32],
mask2 < INT[32],
shiftout < INT[32],
RightOpBus < INT[32],
Control
insert < BOOL,
Output
sBus > INT[32],
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
EvalSimple
compositemask: BitOps.BitDWord;
IF PhB THEN { -- no insert => (shiftout AND mask1)
IF insert THEN { -- use compositemask to select between shiftout and OpRightBus
compositemask ← BitOps.DXOR[mask1, mask2];
sBus ← BitOps.DOR[
BitOps.DAND[shiftout, compositemask],
BitOps.DAND[RightOpBus, BitOps.DNOT[compositemask, 32]]
];
}
ELSE { -- just mask shiftout
compositemask ← mask1;
sBus ← BitOps.DAND[shiftout, compositemask];
};
};
ENDCELL;
EUField: CELL [
Large Buses
LeftOpBus < INT[32],
RightOpBus < INT[32],
cBus < INT[32], -- only for updating field
ConstBus < INT[32], -- only for updating kBusAB
sBus > INT[32],
Mux selectors
EUAluOpAB < EnumType["Dragon.ALUOps"], -- sent on 1A, used during 2B. Not latched by EU.
writeFieldBA < BOOL, -- provided by the RAM
Reject
rejectBA < BOOL,
Timing and housekeeping interface
PhA, PhB<BOOL,
ResetAB<BOOL,
Vdd, Gnd, PadVdd, PadGnd<BOOL
]
Expand
Internal glue
mask1: INT[32];
mask2: INT[32];
shiftout: INT[32];
insert: BOOL;
fdshift: INT[6];
fdmask: INT[6];
mask generation
FieldDescr: FUFieldDescr[];
MaskGen1: FUMaskGen[mask: mask1, width: fdmask];
MaskGen2: FUMaskGen[mask: mask2, width: fdshift];
shifter: FUShifter[];
merge: FUMerge[]
ENDCELL