DIRECTORY CMosB, CoreCreate, CoreIO, PadFrame, PGA176; IFUStdPadFrameImpl: CEDAR PROGRAM IMPORTS CoreCreate, CoreIO, PadFrame, PGA176 = BEGIN OPEN CoreCreate, PGA176; CreateFullIFU: PUBLIC PROC [props: Properties _ NIL] RETURNS [cellType: CellType] = { padKBus: Wire _ Seq["Pad-XBus", 32]; padIpData: Wire _ Seq["Pad-IPData", 32]; padDpFault: Wire _ Seq["Pad-DPFaultB", 4]; padDpCmd: Wire _ Seq["Pad-DPCmnd2BAA", 8]; padAluOp: Wire _ Seq["Pad-EUAluOp2ABB", 4]; padCondSel: Wire _ Seq["Pad-EUCondSel2ABB", 4]; public: Wire _ WireList[LIST[ -- should be the same as IFUPublic.IfuInitializedPublic[] padKBus, padIpData, padDpFault, padDpCmd, padAluOp, padCondSel, "PadVdd", "PadGnd", "Vdd", "Gnd", "Vbb", "Pad-PhA", "Pad-PhB", "Pad-IPRejectB", "Pad-IPFaultingB", "Pad-NewFetchBAA", "Pad-ResetAB", "Pad-RescheduleAB", "Pad-DShIn", "Pad-DShOut", "Pad-DShA", "Pad-DShB", "Pad-DShRd", "Pad-DShWt", "Pad-DPRejectB", "Pad-UserMode2BAA", "Pad-EUCondition2B", "Pad-EURdFromPBus3ABB", "Pad-EUWriteToPBus3ABB" ]]; xBus: Wire _ Seq["XBus", 32]; ipAddr: Wire _ Seq["IPAddr", 32]; ipData: Wire _ Seq["IPData", 32]; dpFault: Wire _ Seq["DPFaultB", 4]; dpCmd: Wire _ Seq["DPCmnd2BAA", 8]; aluOp: Wire _ Seq["EUAluOp2ABB", 4]; condSel: Wire _ Seq["EUCondSel2ABB", 4]; onlyInternal: Wire _ WireList[LIST[ -- for Cabbage xBus, ipAddr, ipData, dpFault, dpCmd, aluOp, condSel, "PhA", "PhB", "NotPhA", "NotPhB", "IPRejectB", "IPFaultingB", "NewFetchBAA", "ResetAB", "RescheduleAB", "DShIn", "DShOut", "DShA", "DShB", "DShRd", "DShWt", "DPRejectB", "UserMode2BAA", "KPadsOut3BA", "KPadsIn4Ac", "NotKPadsIn4Ac", "EUCondition2B", "EURdFromPBus3ABB", "EUWriteToPBus3ABB", "Stage3ANormalBA", "NotDPRejectBA" ]]; pga: PGADescr _ MakePGA176[]; -- this puts the power pads SetPos[pga, pga176.left+9]; SPad[pga, "Pad-IPRejectB", $In, ["toChip", "IPRejectB"]]; SPad[pga, "Pad-IPFaultingB", $In, ["toChip", "IPFaultingB"]]; SPad[pga, "Pad-NewFetchBAA", $Gate2Out, ["fromChip", "NewFetchBAA"], ["enWA", "PhA"]]; SPad[pga, "Pad-ResetAB", $In, ["toChip", "ResetAB"]]; SPad[pga, "Pad-RescheduleAB", $In, ["toChip", "RescheduleAB"]]; SPad[pga, "Vbb", $Analog]; SPad[pga, "Pad-DShIn", $In, ["toChip", "DShIn"]]; SPad[pga, "Pad-DShOut", $Out, ["fromChip", "DShOut"]]; SPad[pga, "Pad-PhA", $Clk, ["Clock", "PhA"], ["nClock", "NotPhA"]]; SPad[pga, "Pad-PhB", $Clk, ["Clock", "PhB"], ["nClock", "NotPhB"]]; SPad[pga, "Pad-DShA", $In, ["toChip", "DShA"]]; SPad[pga, "Pad-DShB", $In, ["toChip", "DShB"]]; SPad[pga, "Pad-DShRd", $In, ["toChip", "DShRd"]]; SPad[pga, "Pad-DShWt", $In, ["toChip", "DShWt"]]; SetPos[pga, pga176.bottom]; FOR index: NAT IN [0..32) DO SPad[pga, padKBus[index], $IOTstIO, ["toChip", xBus[index]], ["fromChip", xBus[index]], ["phA", "PhA"], ["enWA", "KPadsOut3BA"], ["phB", "PhB"], ["enWB", "Vdd"], ["enRd", "KPadsIn4Ac"], ["disRd", "NotKPadsIn4Ac"], ]; ENDLOOP; SetPos[pga, pga176.right+8]; SPad[pga, "Pad-EUWriteToPBus3ABB", $Out, ["fromChip", "EUWriteToPBus3ABB"]]; SPad[pga, "Pad-EURdFromPBus3ABB", $Out, ["fromChip", "EURdFromPBus3ABB"]]; SPad[pga, "Pad-EUCondition2B", $In, ["toChip", "EUCondition2B"]]; FOR i: NAT IN [0..padCondSel.size) DO SPad[pga, padCondSel[i], $Out, ["fromChip", condSel[i]]]; ENDLOOP; FOR i: NAT IN [0..padAluOp.size) DO SPad[pga, padAluOp[i], $Out, ["fromChip", aluOp[i]]]; ENDLOOP; FOR i: NAT IN [0..padDpCmd.size) DO SPad[pga, padDpCmd[i], $Gate4Out, ["fromChip", dpCmd[i]], ["enWA", "PhA"], ["enWB", "NotDPRejectBA"], ["enWC", "Stage3ANormalBA"]]; ENDLOOP; SPad[pga, "Pad-UserMode2BAA", $Out, ["fromChip", "UserMode2BAA"]]; SPad[pga, "Pad-DPRejectB", $In, ["toChip", "DPRejectB"]]; FOR i: NAT IN [0..padDpFault.size) DO SPad[pga, padDpFault[i], $In, ["toChip", dpFault[i]]]; ENDLOOP; SetPos[pga, pga176.top]; FOR index: NAT DECREASING IN [0..32) DO SPad[pga, padIpData[index], $IOTst, ["toChip", ipData[index]], ["fromChip", ipAddr[index]], ["phA", "PhA"], ["enWA", "Vdd"], ["phB", "PhB"], ["enWB", "Gnd"]]; ENDLOOP; cellType _ PadFrame.CreatePadFrame[ public: public, onlyInternal: onlyInternal, innerInstance: Instance[MakeInner[] ], pads: pga.pads, params: [ horizLayer: "metal", vertLayer: "metal2", nbPadsX: pga176.size, nbPadsY: pga176.size, library: "CommonPads.dale", centerDisplacement: [0*CMosB.lambda, 0*CMosB.lambda]], name: "IFU", props: props ]; }; fakeInner: BOOL _ FALSE; MakeInner: PROC [] RETURNS [cellType: CellType] ~ { ct: CellType _ CoreIO.RestoreCellType["Bind"]; cellType _ IF fakeInner THEN Cell[name: "Inner", public: ct.public, instances: NIL] ELSE ct; }; END. DAUser Install PadFrame Run -a PGA176Impl Run -a IFUStdPadFrameImpl _ IFUStdPadFrameImpl.fakeInner _ FALSE _ &ct _ IFUStdPadFrameImpl.CreateFullIFU[] XIFUStdPadFrameImpl.mesa Copyright Σ 1985, 1986, 1987 by Xerox Corporation. All rights reserved. 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