EUInner.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier April 15, 1986 11:32:41 am PST
Last Edited by: Louis Monier March 11, 1987 6:37:07 pm PST
DIRECTORY Core, EUUtils, Sisyph;
EUInner: CEDAR DEFINITIONS =
BEGIN
CreateFullEU: PROC [cx: Sisyph.Context, props: Core.Properties ← NIL] RETURNS [cellType: Core.CellType];
CreateEUInner: PROC [cx: Sisyph.Context] RETURNS [Core.CellType];
CreateControl: PROC [cx: Sisyph.Context] RETURNS [Core.CellType];
CreateRamControl: PROC [] RETURNS [Core.CellType];
CreateSCControl: PROC [cx: Sisyph.Context] RETURNS [Core.CellType];
CreateDPControl: PROC [] RETURNS [Core.CellType];
CreateDataPath: PROC [cx: Sisyph.Context] RETURNS [Core.CellType];
CreateEURam:
PROC [cx: Sisyph.Context]
RETURNS [Core.CellType];
-- (ramA, ramB, cBus)[0..32), (selA, selB, selC)[0..40), (selALow, selBLow, selCLow)[0..4), Vdd, Gnd, nPrech
CreateRamArray:
PROC [cx: Sisyph.Context]
RETURNS [cellType: Core.CellType];
-- (naBit, bBit, cBit, ncBit)[0..32)[0..4), (selA, selB, selC)[0..nRows), Vdd, Gnd
-- The order of bits here is the wrong Mesa order, i.e. the high-order bit is 0. However, the carry out was called c32, for the sake of confusion. It is renamed carryOut.
-- The "zero" bit out of the ALU is not what you think: it is p0.31 which is obtained at the top of the tree iff a-b=0, i.e. a+~b+1=0, i.e. a+~b=11111...111, i.e a=b. Thus, this bit is meaningful only after a VSub!
CreateALU: PROC [cx: Sisyph.Context] RETURNS [Core.CellType];
Tree: PUBLIC PROC RETURNS [Core.Wire];
CreateFieldUnit:
PROC [cx: Sisyph.Context]
RETURNS [Core.CellType];
-- (left, st2A, r2B, cBus, fuOut)[0..32), insert, (mask, shift)[0..6), sh[0..33)
CreateBarrelShifter:
PROC [cx: Sisyph.Context]
RETURNS [cellType: Core.CellType];
-- shOut[0..32), sh[0..33), pass, (left, st2A, r2B, cBus, fuOut)[0..32), Vdd, Gnd
CreateMask:
PROC [cx: Sisyph.Context]
RETURNS [cellType: Core.CellType];
-- mask[0..6), shift[0..6), (m1, m2, st2A, r2B, cBus, fuOut)[0..32), Vdd, Gnd,
CreateCompose:
PROC [cx: Sisyph.Context]
RETURNS [cellType: Core.CellType];
-- Vdd, Gnd, insert, (st2A, r2B, cBus, fuOut, shOut, m1, m2)[0..32)
CreateReg: PROC [regIndex: EUUtils.PipeRange, cx: Sisyph.Context] RETURNS [cellType: Core.CellType];
CreatePDriver: PROC [cx: Sisyph.Context] RETURNS [cellType: Core.CellType];
CreatekRegAndShift: PROC [cx: Sisyph.Context] RETURNS [Core.CellType];
END.