EU4.log
Last Edited by: Louis Monier April 24, 1987 2:55:20 pm PDT
4/21:
Transistor-level simulation (memory on wires) of ZeroAndOne, DBusTest, WiresTest, SanityCheck, ALUTest, FUTest(stopped at 403), RamTest(stopped at 1185, no disk left)
Try to DRC of an older layout (1 day, ALU is different) with Dracula... finally DRC fails to run
4/22:
DRC broke again a number of times. New tape from VTI expected.
No DRC with CD24 and Genista broken in 7.0: no DRC available!
ClusterEU (EU at transistor level+IFU and Cache at top-level) ...
4/23:
DRC broke again. CJ modified CIF generation to explode atomic objects. Then no space on Vax.
Raw extract OK, sanity check passed. RBruce machine was too small.
New raw extract.
Cluster failed because of a check on DShA and DShB which contradicts the purge of the Dbus ShReg during reset. Fixed high-level simulation proc.
4/24:
Raw extracted EU4 passed: ZeroAndOne, Sanity, DBusTest, WiresTest, ALUTest(563), FUTest(59), RamTest.
Still left to do:
Plot EULayout.dale
Visual check of power pads
DRC of EULayout.dale
EUSim of Raw EU with no dynamic memory on wires
ClusterEU
ClusterRawEU
Static
MintCheck
Create and archive EU4Saved.df