C0 W0 17 0 W1 0 1 A0 CoreName r R0 "Vdd" W2 0 1 A0 r R1 "dpRejectB" W3 0 1 A0 r R2 "carryOut" W4 0 1 A0 r R3 "readPBus3AB" W5 0 1 A0 r R4 "carryIn" W6 0 1 A0 r R5 "condition" W7 0 1 A0 r R6 "zero" W8 3 1 A0 r R7 "opL" W9 0 0 WA 0 0 WB 0 0 WC 0 1 A0 r R8 "phB" WD 0 1 A0 r R9 "readPBus" WE 3 1 A0 r RA "opR" WF 0 0 W10 0 0 W11 0 0 W12 5 1 A0 r RB "selCarry" W13 0 0 W14 0 0 W15 0 0 W16 0 0 W17 0 0 W18 0 1 A0 r RC "reject" W19 0 1 A0 r RD "phA" W1A 4 1 A0 r RE "condSel" W1B 0 0 W1C 0 0 W1D 0 0 W1E 0 0 W1F 3 1 A0 r RF "res" W20 0 0 W21 0 0 W22 0 0 W23 0 1 A0 r R10 "Gnd" 2 A0 r R11 "SCControl" A1 Layout a A2 SC R12 "Record" 5 W24 18 0 W1 W7 W25 0 0 W1F WC WD W18 W2 W8 W1A W4 W5 W12 W3 W6 WE W19 W23 W26 5 0 W1 W23 W3 W15 W25 0 C1 W0 5 0 W1 0 2 A0 r R0 A3 PortData l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 0 2 A0 r R13 "I-A" A3 l agg n 0 W4 0 2 A0 r R14 "I-B" A3 l agg n 0 W5 0 2 A0 r R15 "X" A3 l agg d 0 5 A0 r R16 "Xor2" A4 RoseBehave r R16 A5 CoreCutLabel lor 1 R17 "Logic" A6 SCPlacableElement a A7 T A8 SCCellWidth i 6 R18 "LibCell" R19 "CMOSB" R1A "xor2" W27 5 0 W1 W23 W4 WD WC 0 C2 W0 5 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 0 2 A0 r R1B "D" A3 l agg n 0 W4 0 2 A0 r R1C "Q" A3 l agg d 0 W5 0 2 A0 r R1D "S" A3 l agg n 0 5 A0 r R1E "DL" A4 r R1E A5 lor 1 R17 A6 a A7 A8 i 9 R18 R19 R1F "dLatch" W28 9 0 W1 W6 W12 W25 W18 W19 W5 WC W23 0 C3 W0 9 0 W1 0 1 A0 r R0 W2 0 1 A0 r R5 W3 5 1 A0 r RB W4 0 1 A0 r R20 "CBAisZero" W5 0 1 A0 r R21 "CBAisCout" W6 0 0 W7 0 1 A0 r R22 "CINisCAB" W8 0 1 A0 r R23 "invertCin" W9 0 1 A0 r R2 WA 0 1 A0 r RC WB 0 1 A0 r RD WC 0 1 A0 r R4 WD 0 1 A0 r R8 WE 0 1 A0 r R10 1 A0 r R24 "carry" R12 14 WF 19 0 W1 WA W10 0 0 W11 0 0 WB WC W12 0 0 W9 WD W3 W2 W13 0 1 A0 r R25 "carryBA" W14 0 0 W15 0 1 A0 r R26 "carryAB" W16 0 0 W17 0 0 W18 0 0 W19 0 0 WE W1A 5 0 W1 WE W19 W13 WD 0 C2 W1B 5 0 W1 W4 W19 W18 WE 0 C4 W0 5 0 W1 0 2 A9 GivenName a A9 A0 r R0 W2 0 1 A0 r R14 W3 0 1 A0 r R15 W4 0 1 A0 r R13 W5 0 2 A9 a A9 A0 r R10 1 A0 r R27 "nor2" R12 1 W6 4 0 W1 W3 W7 2 2 A0 r R28 "I" A9 a A9 W4 W2 W5 W8 4 0 W1 W5 W7 W3 0 C5 W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 2 2 A0 r R28 A3 ls agg n 0 W4 0 0 W5 0 0 W6 0 2 A0 r R15 A3 l agg d 0 3 A0 r R29 "NormalizedNor2" A4 r R2A "Nor" A5 lor 1 R17 R12 1 W0 W7 5 0 W1 W2 W4 W5 W6 0 C6 W0 5 0 W1 0 1 A0 r R0 W2 0 1 A0 r R10 W3 0 1 A0 r R13 W4 0 1 A0 r R14 W5 0 1 A0 r R15 5 A0 r R2B "Nor2" A4 r R2B A5 lor 1 R17 A6 a A7 A8 i 3 R18 R19 R27 W1C 7 0 W1 WE W15 W14 W9 W5 W18 0 C7 W0 7 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 0 2 A0 r R2C "A" A3 l agg n 0 W4 0 2 A0 r R2D "B" A3 l agg n 0 W5 0 2 A0 r R2E "C" A3 l agg n 0 W6 0 2 A0 r R1B A3 l agg n 0 W7 0 2 A0 r R15 A3 l agg d 0 5 A0 r R2F "A22o2i" A4 r R2F A5 lor 1 R17 A6 a A7 A8 i 5 R18 R19 R30 "a22o2i" W1D 4 0 W1 WE W16 WC 0 C8 W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 0 2 A0 r R28 A3 l agg n 0 W4 0 2 A0 r R15 A3 l agg d 0 5 A0 r R31 "Inv" A4 r R31 A5 lor 1 R17 A6 a A7 A8 i 2 R18 R19 R32 "inv" W1E 4 0 W1 WE W16 WC 0 C8 W1F 4 0 W1 WE W16 WC 0 C8 W20 4 0 W1 WE W16 WC 0 C8 W21 5 0 W1 W5 W14 W4 WE 0 C4 W22 5 0 W1 WE W17 W8 W16 0 C1 W23 5 0 W1 WE W11 W15 WB 0 C2 W24 5 0 W1 W17 W7 W15 WE 0 C9 W0 5 0 W1 0 2 A9 a A9 A0 r R0 W2 0 1 A0 r R15 W3 0 1 A0 r R14 W4 0 1 A0 r R13 W5 0 2 A9 a A9 A0 r R10 1 A0 r R33 "nand2" R12 1 W6 4 0 W1 W2 W7 2 2 A0 r R28 A9 a A9 W4 W3 W5 W8 4 0 W1 W5 W7 W2 0 CA W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 2 2 A0 r R28 A3 ls agg n 0 W4 0 0 W5 0 0 W6 0 2 A0 r R15 A3 l agg d 0 3 A0 r R34 "NormalizedNand2" A4 r R35 "Nand" A5 lor 1 R17 R12 1 W0 W7 5 0 W1 W2 W4 W5 W6 0 CB W0 5 0 W1 0 1 A0 r R0 W2 0 1 A0 r R10 W3 0 1 A0 r R13 W4 0 1 A0 r R14 W5 0 1 A0 r R15 5 A0 r R36 "Nand2" A4 r R36 A5 lor 1 R17 A6 a A7 A8 i 3 R18 R19 R33 W25 4 0 W1 WE W12 W11 0 C8 W26 6 0 W1 W15 W12 W13 W10 WE 0 CC W0 6 0 W1 0 1 A0 r R0 W2 0 1 A0 r R2C W3 0 1 A0 r R37 "nOut" W4 0 1 A0 r R2D W5 0 1 A0 r R38 "selA" W6 0 1 A0 r R10 1 A0 r R39 "invMux2" R12 2 W7 7 0 W1 W3 W2 W8 0 0 W4 W5 W6 W9 7 0 W1 W6 W2 W8 W5 W4 W3 0 C7 WA 4 0 W1 W6 W5 W8 0 C8 W27 5 0 W1 W2 W10 WA WE 0 C4 W29 5 0 W1 W23 W2 W18 WC 0 C2 W2A 10 0 W1 W8 W1A W6 W7 WE W1F W25 WC W23 0 CD W0 10 0 W1 0 1 A0 r R0 W2 3 1 A0 r R7 W3 0 0 W4 0 0 W5 0 0 W6 4 1 A0 r RE W7 0 0 W8 0 1 A0 r R3A "invertCond" W9 0 0 WA 0 0 WB 0 1 A0 r R5 WC 0 1 A0 r R6 WD 3 1 A0 r RA WE 0 0 WF 0 0 W10 0 0 W11 3 1 A0 r RF W12 0 1 A0 r R3B "res0" W13 0 0 W14 0 0 W15 0 1 A0 r R2 W16 0 1 A0 r R8 W17 0 1 A0 r R10 1 A0 r R3C "Condition" R12 17 W18 21 0 W1 W19 0 0 W1A 0 0 WD W15 WB W1B 0 0 W1C 0 0 W1D 0 0 W1E 3 2 A0 r R3D "sel" A9 a A9 W7 W9 WA W16 W1F 0 0 W20 0 1 A0 r R3E "cond" W11 W2 W21 8 2 A0 r R3F "Input" A9 a A9 W17 WC W22 0 1 A0 r R40 "lz" W23 0 1 A0 r R41 "le" W24 0 1 A0 r R42 "ov" W25 0 2 A0 r R15 A9 a A9 W26 0 1 A0 r R43 "il" W17 W6 W27 0 0 W28 0 0 W29 0 0 W17 W2A 6 0 W1 W26 W29 W1B W19 W17 0 CE W0 6 0 W1 0 2 A9 a A9 A0 r R0 W2 0 1 A0 r R15 W3 0 1 A0 r R14 W4 0 1 A0 r R13 W5 0 1 A0 r R44 "I-C" W6 0 2 A9 a A9 A0 r R10 1 A0 r R45 "nand3" R12 1 W7 4 0 W1 W8 3 2 A0 r R28 A9 a A9 W4 W3 W5 W2 W6 W9 4 0 W1 W6 W8 W2 0 CF W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 3 2 A0 r R28 A3 ls agg n 0 W4 0 0 W5 0 0 W6 0 0 W7 0 2 A0 r R15 A3 l agg d 0 3 A0 r R46 "NormalizedNand3" A4 r R35 A5 lor 1 R17 R12 1 W0 W8 6 0 W1 W2 W4 W5 W6 W7 0 C10 W0 6 0 W1 0 1 A0 r R0 W2 0 1 A0 r R10 W3 0 1 A0 r R13 W4 0 1 A0 r R14 W5 0 1 A0 r R44 W6 0 1 A0 r R15 5 A0 r R47 "Nand3" A4 r R47 A5 lor 1 R17 A6 a A7 A8 i 4 R18 R19 R45 W2B 4 0 W1 W17 W27 WB 0 C8 W2C 4 0 W1 W17 W27 WB 0 C8 W2D 5 0 W1 W17 W12 W22 W24 0 C1 W2E 4 0 W1 W17 W27 WB 0 C8 W2F 4 0 W1 W1B W11 W17 0 C11 W0 4 0 W1 0 1 A0 r R0 W2 0 1 A0 r R48 "out" W3 3 1 A0 r R49 "in" W4 0 0 W5 0 0 W6 0 0 W7 0 1 A0 r R10 1 A0 r R4A "IsLisp" R12 3 W8 6 0 W1 W9 0 0 WA 0 0 W3 W2 W7 WB 5 0 W1 W2 W9 WA W7 0 C9 WC 6 0 W1 WA W5 W4 W6 W7 0 CE WD 6 0 W1 W5 W6 W9 W4 W7 0 C12 W0 6 0 W1 0 2 A9 a A9 A0 r R0 W2 0 1 A0 r R14 W3 0 1 A0 r R44 W4 0 1 A0 r R15 W5 0 1 A0 r R13 W6 0 2 A9 a A9 A0 r R10 1 A0 r R4B "or3" R12 1 W7 4 0 W1 W8 3 2 A0 r R28 A9 a A9 W5 W2 W3 W4 W6 W9 4 0 W1 W6 W8 W4 0 C13 W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 3 2 A0 r R28 A3 ls agg n 0 W4 0 0 W5 0 0 W6 0 0 W7 0 2 A0 r R15 A3 l agg d 0 3 A0 r R4C "NormalizedOr3" A4 r R4D "Or" A5 lor 1 R17 R12 1 W0 W8 6 0 W1 W2 W4 W5 W6 W7 0 C14 W0 6 0 W1 0 1 A0 r R0 W2 0 1 A0 r R10 W3 0 1 A0 r R13 W4 0 1 A0 r R14 W5 0 1 A0 r R44 W6 0 1 A0 r R15 5 A0 r R4E "Or3" A4 r R4E A5 lor 1 R17 A6 a A7 A8 i 5 R18 R19 R4B W30 4 0 W1 W17 W27 WB 0 C8 W31 5 0 W1 W23 WC W22 W17 0 C15 W0 5 0 W1 0 2 A9 a A9 A0 r R0 W2 0 1 A0 r R15 W3 0 1 A0 r R14 W4 0 1 A0 r R13 W5 0 2 A9 a A9 A0 r R10 1 A0 r R4F "or2" R12 1 W6 4 0 W1 W7 2 2 A0 r R28 A9 a A9 W4 W3 W2 W5 W8 4 0 W1 W5 W7 W2 0 C16 W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 2 2 A0 r R28 A3 ls agg n 0 W4 0 0 W5 0 0 W6 0 2 A0 r R15 A3 l agg d 0 3 A0 r R50 "NormalizedOr2" A4 r R4D A5 lor 1 R17 R12 1 W0 W7 5 0 W1 W2 W4 W5 W6 0 C17 W0 5 0 W1 0 1 A0 r R0 W2 0 1 A0 r R10 W3 0 1 A0 r R13 W4 0 1 A0 r R14 W5 0 1 A0 r R15 5 A0 r R51 "Or2" A4 r R51 A5 lor 1 R17 A6 a A7 A8 i 4 R18 R19 R4F W32 4 0 W1 W17 W1F W27 0 C8 W33 4 0 W1 W29 W2 W17 0 C11 W34 5 0 W1 W17 W1A W1F W16 0 C2 W35 4 0 W1 W19 WD W17 0 C11 W36 5 0 W1 W17 W20 W8 W1A 0 C1 W37 5 0 W1 W17 W1D W15 W22 0 C1 W38 5 0 W1 W17 WE W3 W1D 0 C1 W39 5 0 W1 W1E W21 W20 W17 0 C18 W0 5 0 W1 0 1 A0 r R0 W2 3 1 A0 r R3D W3 0 0 W4 0 0 W5 0 0 W6 8 1 A0 r R3F W7 0 0 W8 0 0 W9 0 0 WA 0 0 WB 0 0 WC 0 0 WD 0 0 WE 0 0 WF 0 1 A0 r R52 "Output" W10 0 1 A0 r R10 1 A0 r R53 "decoder3" R12 23 W11 20 0 W1 W12 0 0 W13 0 0 W14 0 0 WF W15 0 0 W16 0 0 W17 0 0 W18 0 0 W19 0 0 W1A 0 0 W1B 0 0 W1C 0 0 W2 W1D 0 0 W1E 0 0 W6 W1F 0 0 W20 0 0 W10 W21 5 0 W1 WE W20 W1B W10 0 C19 W0 5 0 W1 0 1 A0 r R0 W2 0 1 A0 r R28 W3 0 1 A0 r R15 W4 0 1 A0 r R54 "EN" W5 0 1 A0 r R10 1 A0 r R55 "3BufferI" R12 2 W6 6 0 W1 W7 0 0 W2 W3 W4 W5 W8 4 0 W1 W5 W4 W7 0 C8 W9 6 0 W1 W5 W2 W3 W4 W7 0 C1A W0 6 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 0 2 A0 r R28 A3 l agg n 0 W4 0 2 A0 r R15 A3 l agg n 0 W5 0 2 A0 r R54 A3 l agg n 0 W6 0 2 A0 r R56 "NEN" A3 l agg n 0 5 A0 r R57 "TstDriver" A4 r R57 A5 lor 1 R17 A6 a A7 A8 i 4 R18 R19 R58 "tstDriver" W22 4 0 W1 W10 W20 WF 0 C8 W23 5 0 W1 WD W20 W17 W10 0 C19 W24 5 0 W1 WC W20 W14 W10 0 C19 W25 5 0 W1 WB W20 W1F W10 0 C19 W26 6 0 W1 W15 W1B W12 W19 W10 0 C1B W0 6 0 W1 0 2 A9 a A9 A0 r R0 W2 0 1 A0 r R13 W3 0 1 A0 r R15 W4 0 1 A0 r R14 W5 0 1 A0 r R44 W6 0 2 A9 a A9 A0 r R10 1 A0 r R59 "nor3" R12 1 W7 4 0 W1 W8 3 2 A0 r R28 A9 a A9 W2 W4 W5 W3 W6 W9 4 0 W1 W6 W8 W3 0 C1C W0 4 0 W1 0 2 A0 r R0 A3 l agg n 0 W2 0 2 A0 r R10 A3 l agg n 0 W3 3 2 A0 r R28 A3 ls agg n 0 W4 0 0 W5 0 0 W6 0 0 W7 0 2 A0 r R15 A3 l agg d 0 3 A0 r R5A "NormalizedNor3" A4 r R2A A5 lor 1 R17 R12 1 W0 W8 6 0 W1 W2 W4 W5 W6 W7 0 C1D W0 6 0 W1 0 1 A0 r R0 W2 0 1 A0 r R10 W3 0 1 A0 r R13 W4 0 1 A0 r R14 W5 0 1 A0 r R44 W6 0 1 A0 r R15 5 A0 r R5B "Nor3" A4 r R5B A5 lor 1 R17 A6 a A7 A8 i 4 R18 R19 R59 W27 6 0 W1 W13 W17 W12 W19 W10 0 C1B W28 5 0 W1 WA W20 W1E W10 0 C19 W29 6 0 W1 W15 W14 W18 W19 W10 0 C1B W2A 6 0 W1 W13 W1F W18 W19 W10 0 C1B W2B 5 0 W1 W9 W20 W1D W10 0 C19 W2C 6 0 W1 W15 W1E W12 W16 W10 0 C1B W2D 5 0 W1 W8 W20 W1C W10 0 C19 W2E 6 0 W1 W13 W1D W12 W16 W10 0 C1B W2F 5 0 W1 W7 W20 W1A W10 0 C19 W30 6 0 W1 W15 W1C W18 W16 W10 0 C1B W31 6 0 W1 W13 W1A W18 W16 W10 0 C1B W32 4 0 W1 W10 W15 W13 0 C8 W33 4 0 W1 W10 W12 W18 0 C8 W34 4 0 W1 W10 W19 W16 0 C8 W35 4 0 W1 W10 W5 W15 0 C8 W36 4 0 W1 W10 W4 W12 0 C8 W37 4 0 W1 W10 W3 W19 0 C8 W3A 4 0 W1 W17 W15 W25 0 C8