EUSoftCard.tioga
Copyright © 1987 by Xerox Corporation. All rights reserved.
Last Edited by: Louis Monier March 30, 1987 6:36:51 pm PST
This documents explains how to use the debug features for the EU3. The EU3 is the version of the EU sent to fab in November 86 and received back in January 87. Its DBus is explicitely matched to the IFU DBus, and is not compatible with the DBus for the Jun87 Dragon.
The EU3's datapath contains a 32-bit shift register controlled by an independent 2-phase clock, connected to the cBus (an internal bus). Every datapath register can be read or written from the cBus.
The following wires are used for debugging the EU3:
DHold -- prevents any state change in the EU3 (unused)
DShA, DShB -- the clocks for the shift register
DShIn, DShOut -- the extremities of the shift register: into LSB, out of MSB
DShRd, DShWt -- controls transfer between a register and the shift register
DStAd[0..4) -- specifies which register to read or write
The following registers (11 altogether) are accessible through the DBus (with their DStAd):
left (0), right (1) -- operands for ALU and field unit
st2A (2), st2B (3), st3A (4) -- pipeline for the data to be sent to Cache (store)
r2B (7), r3A (8), r3B (9) -- pipeline for the output of the ALU
kReg (5) -- a collection of control bits sent by the IFU
field (6) -- the field descriptor
dataIn (10) -- data back from the Cache
carryBA (15) -- the carry (EU4 and up only)
All registers are 32-bit and most of them are interpreted as 32-bit values. Two exceptions:
field (6) is of type DragOpsCross.FieldDescriptor flushed in the MSB, i.e.
field[0] is insert
field[1..7) is mask
field[7..13) is shift
field[13..32) are reserved bits, which must be set to zero
kReg (5) is a collection of control bits sent by the IFU
kReg[0..8) is the A address for the register file (left read port)
kReg[8..16) is the B address for the register file (right read port)
kReg[16..24) is the C address for the register file (write port)
kReg[24) specifies the source for the `st3A' register (1 bit)
kReg[25..27) specifies the source for the `left' register (2 bits)
kReg[27..30) specifies the source for the `right' register (3 bits)
kReg[30..32) specifies the source for the `st2A' register (2 bits)
Timing sequences
The semi-colon indicates sequentiality, while the comma separates instructions which can be executed in any order.
During any debugging, unless specified otherwise, we suppose that DHold is asserted and that both PhA and PhB are low. Also the initial values of DShA, DShB, DShWt and DShRd are low.
Shifting a value into the shift register and reading the former content
DShA ← L, DShB ← L;
FOR i:
NAT
IN [0..32)
DO
-- 0 is the high-order bit
DShIn ← newVal[31-i]; -- shift in lsb first
DShB ← H;
oldVal[i] ← DShOut; -- shift out msb first
DShB ← L;
DShA ← H;
DShA ← L;
ENDLOOP;
DShA ← L, DShB ← L;
Setting a register to a value
shift the value in the shift register;
DShWt ← H;
DStAd ← address of this particular register;
DShWt ← L;
Reading the value of a register
DShRd ← H;
DStAd ← address of this particular register;
DShRd ← L;
shift out the value of the shift register;
Reading the RAM
load kReg with
kReg.aAdr ← the address you wish to read
kReg.leftSource ← ramA (right now, that's 0)
PhA ← H; -- select line is high, the read happens
PhA ← L; -- the value is latched inside `left'
read out the value of `left'
Writing the RAM
load the value into r3B;
load kReg so that kReg.cAdr ← the address you wish to write to;
DStAd ← r3B, DShRd ← H; -- the value will be on the cBus (could I put it form ShReg?)
PhA ← H; -- select line is high, the write happens
PhA ← L; -- write is finished
Accessing the carry
The carry can be read or written just like any other register. It is mapped to the high-order bit (0) of the shift register.