DIRECTORY  
Core, CoreFlat, Dragon, EUArith, EUUtils, IO, Rope, Rosemary, RosemaryUser, Ports, TerminalIO;

EUSim: CEDAR PROGRAM
IMPORTS CoreFlat, EUArith, EUUtils, IO, Rosemary, RosemaryUser, Ports, TerminalIO = 
BEGIN
ROPE: TYPE = Rope.ROPE;
nbPhases: INT _ 0;

Vdd, Gnd, PadVdd, PadGnd, PhA, PhB,
DPRejectB, DPData, 	-- 32 bits
KBus, 			-- 32 bits
EURdFromPBus3AB, EUWriteToPBus3AB, 
EUAluOp2AB, 	-- 4 bits 
EUCondSel2AB, 	-- 4 bits 
EUCondition2B, 
DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT _ LAST[NAT];

Initialize: PROC [p: Ports.Port, public: Core.Wire] = {
InitializePublic[public];
p[DPRejectB].b _ FALSE;
p[DShA].b _ p[DShB].b _ TRUE;	-- hack to clean up the ShReg.
p[DShRd].b _ p[DShWt].b _ p[DShIn].b _ p[DHold].b _ FALSE;
p[DStAd].c _ 0;
p[EUCondSel2AB].c _ 0;				-- false
p[EUAluOp2AB].c _ ORD[Dragon.ALUOps[Or]];		-- 0
p[EURdFromPBus3AB].b _ FALSE;	-- don't read data from PBus
p[EUWriteToPBus3AB].b _ FALSE;	-- and don't write onto PBus during PhB
p[DShOut].b _ FALSE;
p[DShOut].d _ none;
p[EUCondition2B].b _ FALSE;
p[EUCondition2B].d _ none;
p[KBus].d _ none;
p[DPData].d _ none;
};
InitializePublic: PROC [public: Core.Wire] = {
[Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData] _ Ports.PortIndexes[public, "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "DPRejectB", "DPData"];
[KBus, EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, EUCondSel2AB, EUCondition2B] _ Ports.PortIndexes[public, "KBus", "EURdFromPBus3AB", "EUWriteToPBus3AB", "EUAluOp2AB", "EUCondSel2AB", "EUCondition2B"];
[DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd] _ 
Ports.PortIndexes[public, "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", "DStAd"];
[] _ Rosemary.SetFixedWire[public[Vdd], H];
[] _ Rosemary.SetFixedWire[public[Gnd], L];
[] _ Rosemary.SetFixedWire[public[PadVdd], H];
[] _ Rosemary.SetFixedWire[public[PadGnd], L];
[] _ Ports.InitTesterDrive[public[PhA], force];
[] _ Ports.InitTesterDrive[public[PhB], force];
[] _ Ports.InitTesterDrive[public[DPRejectB], force];
[] _ Ports.InitPort[public[DPData], lc];
[] _ Ports.InitTesterDrive[public[DPData], expect];
[] _ Ports.InitPort[public[KBus], lc];
[] _ Ports.InitTesterDrive[public[KBus], force];
[] _ Ports.InitTesterDrive[public[EURdFromPBus3AB], force];
[] _ Ports.InitTesterDrive[public[EUWriteToPBus3AB], force];
[] _ Ports.InitPort[public[EUAluOp2AB], c];
[] _ Ports.InitTesterDrive[public[EUAluOp2AB], force];
[] _ Ports.InitPort[public[EUCondSel2AB], c];
[] _ Ports.InitTesterDrive[public[EUCondSel2AB], force];
[] _ Ports.InitTesterDrive[public[EUCondition2B], expect];
[] _ Ports.InitTesterDrive[public[DShA], force];
[] _ Ports.InitTesterDrive[public[DShB], force];
[] _ Ports.InitTesterDrive[public[DShRd], force];
[] _ Ports.InitTesterDrive[public[DShWt], force];
[] _ Ports.InitTesterDrive[public[DShIn], force];
[] _ Ports.InitTesterDrive[public[DHold], force];
[] _ Ports.InitPort[public[DStAd], c];
[] _ Ports.InitTesterDrive[public[DStAd], force];
[] _ Ports.InitTesterDrive[public[DShOut], none];
};

ExerciseRose: PUBLIC PROC [ct: Core.CellType, cutSets: LIST OF ROPE _ NIL] RETURNS [tester: RosemaryUser.Tester] = {
InitializePublic[ct.public];
tester _ RosemaryUser.TestProcedureViewer[
cellType: ct, 
testButtons: LIST["EUTest", "Sanity Check", "RamTest", "ALUTest", "FUTest"], 
name: "EUTest", 
displayWires: RosemaryUser.DisplayPortLeafWires[ct], 
cutSet: CoreFlat.CreateCutSet[labels: cutSets],
steady: FALSE];
};

constAdr: NAT _ EUUtils.constAdr;
junkAdr: NAT _ EUUtils.junkAdr;
IFUAdr: NAT _ EUUtils.IFUAdr;
fieldAdr: NAT _ EUUtils.fieldAdr;
Phase: TYPE = {A, B};
DoPh: PROC [p: Ports.Port, Eval: PROC, ph: Phase] = {
nbPhases _ nbPhases+1;
IF PhA=0 AND PhB=0 THEN ERROR;		-- port indexes not initialized
IF ph=A AND p[DPData].d=force THEN ERROR;
p[PhA].b _ ph=A;	p[PhB].b _ ph=B;	Eval[];
p[PhA].b _ FALSE;	p[PhB].b _ FALSE;	Eval[ ! Ports.CheckError => RESUME];
};
Ignore: PROC [p: Ports.Port, port: NAT] ~ {p[port].d _ none};
Force: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d _ force; p[port].lc _ val};
Expect: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d _ expect; p[port].lc _ val};
ReadPBus: PROC [p: Ports.Port] ~ {
p[EURdFromPBus3AB].b _ TRUE;	
p[EUWriteToPBus3AB].b _ FALSE;
};
WritePBus: PROC [p: Ports.Port] ~ {
p[EURdFromPBus3AB].b _ FALSE;	
p[EUWriteToPBus3AB].b _ TRUE;
};
IgnorePBus: PROC [p: Ports.Port] ~ {
p[EURdFromPBus3AB].b _ FALSE;	
p[EUWriteToPBus3AB].b _ FALSE;
};
PackK: PROC [a, b: NAT _ constAdr, c: NAT _ junkAdr, st3AisC: BOOL _ FALSE, 
aluL, aluR, st2A: NAT _ 0] RETURNS [k: LONG CARDINAL] ~ {
k _ (((((LONG[a]*256+LONG[b])*256+LONG[c])*2+(IF st3AisC THEN 1 ELSE 0))*4+aluL)*8+aluR)*4+st2A;
};
WriteInRam: PROC [p: Ports.Port, Eval: PROC, ad: NAT, val: LONG CARDINAL] ~ {
Force[p, KBus, PackK[c: ad]];	-- load c address in kReg
ReadPBus[p];
Force[p, DPData, val];
DoPh[p, Eval, B];									-- 0B: kReg _ ad; dataIn _ val
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 1A: ram[ad] _ val
};
ReadFromRam: PROC [p: Ports.Port, Eval: PROC, ad: NAT, val: LONG CARDINAL, m: LONG CARDINAL _ 01234567H] ~ {
Force[p, KBus, PackK[b: ad, st2A: 0]];	-- load b address in kReg
ReadPBus[p];
Force[p, DPData, m];		-- to detect no drive on PBus
DoPh[p, Eval, B];									-- 0B: kReg _ ad
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 1A: st2A _ ram[ad]
Force[p, KBus, PackK[]];
Ignore[p, DPData];
DoPh[p, Eval, B];									-- 1B: st2B _ st2A
Ignore[p, KBus];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 2A: st3A _ st2B
Force[p, KBus, PackK[]];
WritePBus[p];
Expect[p, DPData, val];
DoPh[p, Eval, B];									-- 2B: PBus _ st3A = val ???
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 3A: just for sync.
};
FromPtoK: PROC [p: Ports.Port, Eval: PROC, val: LONG CARDINAL] ~ {
Force[p, KBus, PackK[c: IFUAdr]];	-- cBus->IFU on next PhA
ReadPBus[p];
Force[p, DPData, val];
DoPh[p, Eval, B];									-- Cycle 0: dataIn _ val
Expect[p, KBus, val];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- Cycle 1: KBus _ cBus _ val
IgnorePBus[p];
};
ALUOp: PROC [p: Ports.Port, Eval: PROC, op: Dragon.ALUOps, opL, opR, res: LONG CARDINAL, cc: Dragon.CondSelects _ False, cond: BOOL _ FALSE] ~ {
lAd: NAT = 1;
rAd: NAT = 3;
WriteInRam[p, Eval, lAd, opL];
WriteInRam[p, Eval, rAd, opR];
p[EURdFromPBus3AB].b _ FALSE;
Force[p, KBus, PackK[a: lAd, b: rAd]];
Ignore[p, DPData];
DoPh[p, Eval, B];									-- 0B: aAdr _ lAd, bAdr _ rAd
p[EUAluOp2AB].c _ ORD[op];
Ignore[p, KBus];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 1A: opL _ ram[lAd]; opR _ ram[rAd]
p[EUCondSel2AB].c _ ORD[cc];
p[EUCondition2B].b _ cond;
p[EUCondition2B].d _ expect;
p[DShOut].b _ FALSE;
p[DShOut].d _ expect;
Force[p, KBus, PackK[]];
Ignore[p, DPData];
DoPh[p, Eval, B];									-- 1B: r2B _ opL op opR
TerminalIO.WriteF["ALU, phase %g: %g (%g) %g -> %g", IO.card[nbPhases], IO.card[opL], IO.rope[opName[op]], IO.card[opR], IO.card[res]];
TerminalIO.WriteF[" cc: %g\n", IO.int[ORD[cc]]];
p[EUCondSel2AB].c _ 0;
p[EUCondition2B].b _ FALSE;
p[EUCondition2B].d _ none;
p[DShOut].d _ none;
Ignore[p, KBus];
Expect[p, DPData, res];
DoPh[p, Eval, A];									-- 2A: PBus _ r2B
p[EUAluOp2AB].c _ 0;
};
FUOp: PROC [p: Ports.Port, Eval: PROC, leftW, rightW, mask, shift: LONG CARDINAL, insert: BOOL _ FALSE] ~ {
fd: NAT _ ((IF insert THEN 1 ELSE 0)*64+mask)*64+shift;
res: LONG CARDINAL _ EUArith.FieldOp[leftW, rightW, fd];
TerminalIO.WriteF["FU, phase %g, mask: %g, shift: %g, insert: %g\n", IO.card[nbPhases], IO.card[mask], IO.card[shift], IO.bool[insert]];
WriteInRam[p, Eval, fieldAdr, LONG[fd]];	-- field_fd
WriteInRam[p, Eval, 1, leftW];		-- ram[0]_leftW
WriteInRam[p, Eval, 2, rightW];		-- ram[1]_rightW

Force[p, KBus, PackK[a: 1, b: 2, aluR: 4]]; -- right_field; left_leftW; st2A_rightW
Ignore[p, DPData];
DoPh[p, Eval, B];							-- 0B: load operand addresses
p[EUAluOp2AB].c _ ORD[Dragon.ALUOps[FOP]];
Ignore[p, KBus];
Ignore[p, DPData];
DoPh[p, Eval, A];							-- 1A: read ram
Force[p, KBus, PackK[]];
Ignore[p, DPData];
DoPh[p, Eval, B];							-- 1B: field unit is active
Ignore[p, KBus];
Expect[p, DPData, res];
DoPh[p, Eval, A];							-- 2A: PBus _ r2B
};
SanityCheck: RosemaryUser.TestProc = {
FromPtoP2: PROC [val: LONG CARDINAL] ~ {
Force[p, KBus, PackK[st3AisC: TRUE]];	-- st3A _ cBus on next PhA
ReadPBus[p];
Force[p, DPData, val];
DoPh[p, Eval, B];									-- 0B: dataIn _ val
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 1A: st3A _ cBus _ dataIn (val)
Force[p, KBus, PackK[]];
WritePBus[p];
Expect[p, DPData, val];
DoPh[p, Eval, B];									-- 1B: PBus _ st3A = val ???
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 2A: just for sync.
};
FromPtoP4: PROC [val: LONG CARDINAL] ~ {
Force[p, KBus, PackK[st2A: 2]];	-- st2A _ cBus on next PhA
ReadPBus[p];
Force[p, DPData, val];
DoPh[p, Eval, B];									-- 0B: dataIn _ val
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 1A: st2A _ cBus _ val
Force[p, KBus, PackK[]];
IgnorePBus[p];
Force[p, DPData, 01234567H];	-- to eliminate old (good) value on PBus
DoPh[p, Eval, B];									-- 1B: st2B _ st2A
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 2A: st3A _ st2B
Force[p, KBus, PackK[]];
WritePBus[p];
Expect[p, DPData, val];
DoPh[p, Eval, B];									-- 2B: PBus _ st3A = val ???
Ignore[p, KBus];
IgnorePBus[p];
Ignore[p, DPData];
DoPh[p, Eval, A];									-- 3A: just for sync.
};
Initialize[p, cellType.public];
FromPtoP4[000000000H]; FromPtoP4[0AAAAAAAAH]; FromPtoP4[055555555H];
FromPtoP4[0FFFFFFFFH]; FromPtoP4[02BAD2BADH];
FromPtoP2[000000000H]; FromPtoP2[0AAAAAAAAH]; FromPtoP2[055555555H];
FromPtoP2[0FFFFFFFFH]; FromPtoP2[02BAD2BADH];
FromPtoK[p, Eval,000000000H]; FromPtoK[p, Eval,0AAAAAAAAH]; 
FromPtoK[p, Eval,055555555H]; FromPtoK[p, Eval,0FFFFFFFFH]; 
FromPtoK[p, Eval,02BAD2BADH];
};
RamTest: RosemaryUser.TestProc = {
CheckRamBlock: PROC [from, to: NAT] ~ {
FOR i: NAT IN [from..to) DO
WriteInRam[p, Eval, i, 55555555H];
ENDLOOP;
FOR i: NAT IN [from..to) DO
ReadFromRam[p, Eval, i, 55555555H, i]; 
WriteInRam[p, Eval, i, 0AAAAAAAAH];
ENDLOOP;
FOR i: NAT IN [from..to) DO
ReadFromRam[p, Eval, i, 0AAAAAAAAH, i];
ENDLOOP;
};
Initialize[p, cellType.public];
CheckRamBlock[0, 4];
ReadFromRam[p, Eval, constAdr,	0];
ReadFromRam[p, Eval, constAdr+1,	1];
ReadFromRam[p, Eval, constAdr+2,	2];
ReadFromRam[p, Eval, constAdr+3,	3];
};

ALUTest: RosemaryUser.TestProc = {
ResetCarry: PROC ~ {TestALU[LAdd, 0, 0, 0]};
SetCarry: PROC ~ {TestALU[UAdd, 0FFFFFFFFH, 000000001H, 0]};
TestALU: PROC [op: Dragon.ALUOps, opL, opR, res: LONG CARDINAL, cc: Dragon.CondSelects _ False, cond: BOOL _ FALSE] ~ {
ALUOp[p, Eval, op, opL, opR, res, cc, cond];
};
TestAdd: PROC [op: Dragon.ALUOps] ~ {
IF op#SAdd AND op#UAdd AND op#VAdd AND op#LAdd AND op#VAdd2 THEN ERROR;
ResetCarry[];
TestALU[op, 000000000H,000000000H,000000000H];
TestALU[op, 000000001H,000000002H,000000003H];
TestALU[op, 00FFFFFFFH,000000001H,010000000H];
TestALU[op, 012345678H,087654321H,099999999H];
TestALU[op, 0FFFFFFFFH,000000000H,0FFFFFFFFH];
TestALU[op, 000000000H,0FFFFFFFFH,0FFFFFFFFH];
TestALU[op, 000000001H,0FFFFFFFFH,000000000H];
ResetCarry[];
};
TestSub: PROC [op: Dragon.ALUOps] ~ {
IF op#SSub AND op#USub AND op#VSub AND op#LSub THEN ERROR;
TestALU[op, 000000000H,000000000H,000000000H];
TestALU[op, 000000003H,000000002H,000000001H];
TestALU[op, 010000000H,000000001H,00FFFFFFFH];
TestALU[op, 099999999H,087654321H,012345678H];
TestALU[op, 0FFFFFFFFH,000000000H,0FFFFFFFFH];
TestALU[op, 0FFFFFFFFH,0FFFFFFFFH,000000000H];
TestALU[op, 000000000H,0FFFFFFFFH,000000001H];
ResetCarry[];
};
Initialize[p, cellType.public];
TerminalIO.WriteF["New Test\n"];
ResetCarry[];
TestALU[UAdd, 07FFFFFFFH, 000000001H, 080000000H, OvFl, TRUE];
ResetCarry[];
TestALU[UAdd, 07FFFFFFFH, 000000000H, 07FFFFFFFH, OvFl, FALSE];
ResetCarry[];
TestALU[BndChk, 000000000H, 000000001H, 000000000H, BC, FALSE];
ResetCarry[];
TestALU[BndChk, 000000002H, 000000001H, 000000002H, BC, TRUE];
ResetCarry[];
TestALU[BndChk, 000000000H, 000000001H, 000000000H, NotBC, TRUE];
ResetCarry[];
TestALU[BndChk, 000000002H, 000000001H, 000000002H, NotBC, FALSE];
ResetCarry[];
TestALU[USub, 000000000H, 000000001H, 0FFFFFFFFH, LZ, TRUE];
ResetCarry[];
TestALU[UAdd, 000000000H, 000000000H, 000000000H, LZ, FALSE];
ResetCarry[];
TestALU[UAdd, 000000000H, 000000000H, 000000000H, GE, TRUE];
ResetCarry[];
TestALU[USub, 000000000H, 000000001H, 0FFFFFFFFH, GE, FALSE];
ResetCarry[];
TestALU[USub, 000000000H, 000000000H, 000000000H, LE, TRUE];
TestALU[USub, 000000001H, 000000000H, 000000001H, LE, FALSE];

TestALU[USub, 000000001H, 000000000H, 000000001H, NE, TRUE];
TestALU[USub, 000000001H, 000000001H, 000000000H, NE, FALSE];

TestALU[USub, 000000001H, 000000000H, 000000001H, GZ, TRUE];
TestALU[USub, 000000000H, 000000000H, 000000000H, GZ, FALSE];
TestALU[LAdd, 07FFFFFFFH, 000000001H, 080000000H, IL, TRUE];	-- opL=011
TestALU[LAdd, 000000000H, 0FFFFFFFFH, 0FFFFFFFFH, IL, FALSE];	-- all 0 or 1
TestALU[LAdd, 010000000H, 010000000H, 020000000H, IL, TRUE];	-- res=001
TestALU[LAdd, 000000001H, 000000001H, 000000002H, IL, FALSE];	-- all 0
TestALU[LAdd, 07FFFFFFFH, 000000001H, 080000000H, NotIL, FALSE]; -- opL=011
TestALU[LAdd, 000000000H, 0FFFFFFFFH, 0FFFFFFFFH, NotIL, TRUE]; -- all 0 or 1
TestALU[LAdd, 010000000H, 010000000H, 020000000H, NotIL, FALSE]; -- res=001
TestALU[LAdd, 000000001H, 000000001H, 000000002H, NotIL, TRUE];	-- all 0
ResetCarry[];
TestALU[USub, 000000000H, 000000000H, 000000000H, EZ, TRUE];
TestALU[USub, 02BAD2BADH, 02BAD2BADH, 000000000H, EZ, TRUE];
TestALU[USub, 0FFFFFFFFH, 0FFFFFFFFH, 000000000H, EZ, TRUE];
TestALU[USub, 000000001H, 000000000H, 000000001H, EZ, FALSE];
TestALU[USub, 02BAD2BADH, 000000001H, 02BAD2BACH, EZ, FALSE];
TestALU[USub, 000000001H, 000000002H, 0FFFFFFFFH, EZ, FALSE];


TestALU[BndChk, 	000000000H,000000000H,000000000H];
TestALU[BndChk, 	055555555H,000000000H,055555555H];
TestALU[BndChk, 	0AAAAAAAAH,000000000H,0AAAAAAAAH];
TestALU[BndChk, 	0FFFFFFFFH,000000000H,0FFFFFFFFH];
TestALU[Or,	000FF00FFH,00F0F0F0FH,00FFF0FFFH];
TestALU[And, 	000FF00FFH,00F0F0F0FH,0000F000FH];
TestALU[Xor, 	000FF00FFH,00F0F0F0FH,00FF00FF0H];
TestAdd[SAdd];
TestAdd[UAdd];
TestAdd[VAdd];
TestAdd[LAdd];
TestAdd[VAdd2];
TestSub[SSub];
TestSub[USub];
TestSub[VSub];
TestSub[LSub];
TestALU[LAdd, 000000000H, 000000000H, 000000000H, False, FALSE];
TestALU[LAdd, 000000000H, 000000000H, 000000000H, ModeFault, TRUE];
};
FUTest: RosemaryUser.TestProc = {
TestFU: PROC [leftW, rightW, mask, shift: LONG CARDINAL, insert: BOOL _ FALSE] ~ {
FUOp[p, Eval, leftW, rightW, mask, shift, insert];
};
Initialize[p, cellType.public];
FOR shift: NAT IN [0..32] DO
TestFU[leftW: 0F0402010H, rightW: 0AAAAAAAAH, mask: 32, shift: shift];
ENDLOOP;
FOR shift: NAT IN [0..32] DO
TestFU[leftW: 0F0402010H, rightW: 0AAAAAAAAH, mask: shift, shift: 0];
ENDLOOP;
FOR i: NAT IN [0..32] DO
TestFU[leftW: 0F0402010H, rightW: 0AAAAAAAAH, mask: (4*i+19) MOD 33, shift: (3*i+5) MOD 33];
ENDLOOP;
TestFU[leftW: 0F0402010H, rightW: 02BAD2BADH, mask: 0, shift: 0, insert: TRUE];
TestFU[leftW: 0F0402010H, rightW: 02BAD2BADH, mask: 32, shift: 0, insert: TRUE];
TestFU[leftW: 0F0402010H, rightW: 02BAD2BADH, mask: 32, shift: 32, insert: TRUE];
TestFU[leftW: 0F0402010H, rightW: 0AAAAAAAAH, mask: 18, shift: 4, insert: TRUE];
TestFU[leftW: 0F0402010H, rightW: 02BAD2BADH, mask: 21, shift: 12, insert: TRUE];
};

EUTest: RosemaryUser.TestProc = {
};	


opName: ARRAY Dragon.ALUOps OF Rope.ROPE;
opName[Or] _ "Or"; 	opName[And] _ "And";	
opName[VAdd2] _ "VAdd2"; 	opName[BndChk] _ "BndChk";
opName[SAdd] _ "SAdd";	opName[SSub] _ "SSub";
opName[LAdd] _ "LAdd";	opName[LSub] _ "LSub";
opName[Xor] _ "Xor";	opName[res9] _ "res9";
opName[FOP] _ "FOP";	opName[res11] _ "res11";
opName[VAdd] _ "VAdd";	opName[VSub] _ "VSub";	
opName[UAdd] _ "UAdd";	opName[USub] _ "USub";

RosemaryUser.RegisterTestProc["EUTest", 	EUTest];
RosemaryUser.RegisterTestProc["Sanity Check", 	SanityCheck];
RosemaryUser.RegisterTestProc["RamTest", 	RamTest];
RosemaryUser.RegisterTestProc["ALUTest", 	ALUTest];
RosemaryUser.RegisterTestProc["FUTest", 	FUTest];

END.



ShiftDBus: PROC [bitOut: BOOL] ~ {
p[DHold].b _ TRUE;

p[DShA].b _ TRUE;	-- DShIn is sampled
p[DShB].b _ FALSE;
Eval[];

p[DShA].b _ FALSE;	-- DShIn is latched
p[DShB].b _ FALSE;
Eval[];

p[DShA].b _ FALSE;	-- DShOut is driven with a new value
p[DShB].b _ TRUE;
p[DShOut].d _ expect;
p[DShOut].b _ bitOut;
Eval[];

p[DShA].b _ FALSE;	-- Back to normal
p[DShB].b _ FALSE;
p[DShOut].d _ none;
p[DShRd].b _ FALSE;
p[DShWt].b _ FALSE;
p[DHold].b _ FALSE;
p[DStAd].c _ 0;
Eval[];
};

zEUSim.mesa
Copyright c 1985 by Xerox Corporation.  All rights reversed.
Created by Bertrand Serlet July 31, 1985 3:03:17 pm PDT
Last edited by Bertrand Serlet June 8, 1986 5:21:11 pm PDT
Barth, April 16, 1986 3:05:40 pm PST
Louis Monier June 19, 1986 11:54:42 pm PDT
Last Edited by: Louis Monier November 18, 1986 9:17:43 pm PST

Test of EU
-- Invariants
-- On PhA the chip always drives the PBus, so we check that the tester is not driving
-- appropriate clock up
-- both clocks down
-- From PBus to dataIn to cBus to KBus


-- Test procs

-- The minimum expected from a chip
-- A quick test of the RAM
-- Read constants in ROM
-- Test the entire RAM
RamTest: RosemaryUser.TestProc = {
CheckRamBlock: PROC [from, to: NAT] ~ {
FOR i: NAT IN [from..to) DO
WriteInRam[p, Eval, i, 55555555H];
ENDLOOP;
FOR i: NAT IN [from..to) DO
ReadFromRam[p, Eval, i, 55555555H, i]; 
WriteInRam[p, Eval, i, 0AAAAAAAAH];
ENDLOOP;
FOR i: NAT IN [from..to) DO
ReadFromRam[p, Eval, i, 0AAAAAAAAH, i];
ENDLOOP;
};
Initialize[p, cellType.public];
CheckRamBlock[0, 132];
-- Read constants in ROM
ReadFromRam[p, Eval, constAdr, 0];
ReadFromRam[p, Eval, constAdr+1, 1];
ReadFromRam[p, Eval, constAdr+2, 2];
ReadFromRam[p, Eval, constAdr+3, 3];
CheckRamBlock[136, 160];
};
-- may generates a carry
-- may generates a carry
-- OvFl _ (Cout XOR opL[0] XOR opR[0]) XOR res[0], so we need a carry out;
BC _ ~Cout (passed)
-- LZ _ Cout XOR opL[0] XOR opR[0], so we need a carry out; GE _ ~ LZ
-- LE _ EZ OR LZ
IL _ all 3 high-order bits equal (passed)
EZ _ zero, found after a sub at the top of the CLA tree (passed)
Check integrity of aluLeft-> r2B-> pDriver path (passed)
Logic operations (passed)
All additions (passed)
All subtractions (passed)
Constant Conditions (passed)
-- Testing the shifter (no masking) (passed)
-- Testing the mask generator (no shifting) (passed)
-- General Shift and Mask test (passed)
-- With insert (passed)
Κ–

"cedar" style˜
codeš
œ
™
Jšœ
Οm
œ1™<J™7J™:K™$K™*K™=K™—šΟk	œ˜Kš
œ^˜^—J˜•StartOfExpansion[]šΠbnœžœ
ž˜KšžœM˜TKš
ž˜—
head™
Kšžœžœžœ
˜Kšœ
žœ˜K˜Kš
œ#˜#KšœΟc
˜Kšœ ˜Kš
œ#˜#Kšœ
 
˜Kšœ 
˜Kš
œ˜Kšœ7žœžœ
žœ˜GK˜šΟn
œžœ'˜7Kš
œ˜Kšœžœ
˜Kšœžœ ˜<Kšœ4žœ
˜:Kš
œ˜Kšœ ˜"Kšœžœ ˜/Kšœžœ ˜:Kšœžœ '˜FKšœžœ
˜Kš
œ˜Kšœžœ
˜Kš
œ˜Kš
œ˜Kš
œ˜K˜—š‘œžœ˜.Kš
œ›
˜›
Kš
œΝ
˜Ν
š
œ:˜:Kš
œa˜a—Kš
œ+˜+Kš
œ+˜+Kš
œ.˜.Kš
œ.˜.Kš
œ/˜/Kš
œ/˜/Kš
œ5˜5Kš
œ(˜(Kš
œ3˜3Kš
œ&˜&Kš
œ0˜0Kš
œ;˜;Kš
œ<˜<Kš
œ+˜+Kš
œ6˜6Kš
œ-˜-Kš
œ8˜8Kš
œ:˜:Kš
œ0˜0Kš
œ0˜0Kš
œ1˜1Kš
œ1˜1Kš
œ1˜1Kš
œ1˜1Kš
œ&˜&Kš
œ1˜1Kš
œ1˜1K˜—K˜š‘œžœ
žœžœ
žœ
žœžœžœ"˜tKš
œ˜š
œ*˜*Kš
œ˜Kšœ
žœ<˜MKš
œ˜Kš
œ5˜5Kš
œ/˜/Kšœžœ˜—K˜—K˜Kšœ
žœ˜!Kšœ	žœ˜Kšœžœ˜Kšœ
žœ˜!Kšœžœ
˜š‘œžœ‘œžœ˜5K˜K™
Kš	žœžœžœ
žœ ˜?K™UKšžœžœžœ
žœ
˜)K™Kš
œ)˜)J™Kšœžœ
žœžœ˜HK˜—Kš‘œžœžœ˜=Kš
‘œžœžœžœ
žœ*˜cKš
‘œžœžœžœ
žœ+˜eš‘œžœ˜"Kšœžœ˜Kšœžœ
˜K˜—š‘	œžœ˜#Kšœžœ˜Kšœžœ
˜K˜—š‘
œžœ˜$Kšœžœ˜Kšœžœ
˜K˜—š‘œžœžœžœžœžœ˜LKš	œžœžœžœ
žœ˜9Kš
œ	žœžœ	žœžœ	žœžœ˜`K˜—š‘
œžœ‘œžœžœžœ
žœ˜MKšœ ˜7Kš
œ˜š
œ˜Jšœ Πbc ˜8—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜.—K˜—š‘œžœ‘œžœžœžœ
žœžœ
žœ˜lKšœ' ˜@Kš
œ˜šœ ˜3Jšœ ’ ˜*—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜/—Kš
œ˜š
œ˜Jšœ ’ 
˜,—Kš
œ˜š
œ˜Jšœ ’ 
˜,—Kš
œ˜Kš
œ
˜
š
œ˜Jšœ ’ ˜6—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜/—K˜—Kš
œ&™&š‘œžœ‘œžœžœ
žœ˜BKšœ" ˜:Kš
œ˜š
œ˜Jšœ ’ ˜2—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜7—Kš
œ˜K˜—š‘œžœ‘œžœ$žœ
žœ(žœžœ˜
Kšœžœ˜
Kšœžœ˜
Kš
œ˜Kš
œ˜Kšœžœ
˜Kš
œ&˜&š
œ˜Jšœ ’ ˜7—Kšœžœ˜Kš
œ˜š
œ˜Jšœ ’  ˜?—Kšœžœ˜Kš
œ˜Kš
œ˜Kšœžœ
˜Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜1—Kšœ5žœžœžœžœžœ˜‡
Kšœžœžœ˜0Kš
œ˜Kšœžœ
˜Kš
œ˜Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜+—Kš
œ˜K˜—š‘œžœ‘œžœžœ
žœ
žœžœ˜kKš	œžœžœžœžœ˜7Kšœžœ
žœ&˜8Kš	œEžœžœ
žœžœ˜ˆ
Kšœžœ ˜4Kšœ  ˜/Kšœ! ˜1K˜Kšœ, '˜Sš
œ˜Jšœ ’ ˜5—Kšœžœžœ˜*Kš
œ˜š
œ˜Jšœ ’ 
˜'—Kš
œ˜š
œ˜Jšœ ’ ˜3—Kš
œ˜š
œ˜Jšœ ’ ˜)—K˜—K™K™—š
Πlx
™
K™Kš
œ#™#š‘œ˜&š‘	œžœžœ
žœ˜(Kšœžœ ˜@Kš
œ˜š
œ˜Jšœ ’ ˜-—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜;—Kš
œ˜Kš
œ
˜
š
œ˜Jšœ ’ ˜6—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜/—K˜—š‘	œžœžœ
žœ˜(Kšœ  ˜:Kš
œ˜š
œ˜Jšœ ’ ˜-—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜2—Kš
œ˜Kš
œ˜šœ (˜EJšœ ’ 
˜,—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ 
˜,—Kš
œ˜Kš
œ
˜
š
œ˜Jšœ ’ ˜6—Kš
œ˜Kš
œ˜š
œ˜Jšœ ’ ˜/—K˜Kš
œ˜Kšœ	Οf
œ
€
œ
€
˜DKšœ	€
œ
€
˜-Kšœ	€
œ
€
œ
€
˜DKšœ	€
œ
€
˜-Kš
€<˜<Kš
€<˜<Kš
€˜—Kš
œ˜—K™š‘œ˜"š‘
œžœžœ˜'šžœžœ
žœž˜Kš
œ"˜"Kšžœ
˜—šžœžœ
žœž˜Kš
œ'˜'Kš
œ#˜#Kšžœ
˜—šžœžœ
žœž˜Kš
œ'˜'Kšžœ
˜—K˜—Kš
œ˜Kš
œ˜K™Kš
œ"˜"Kš
œ$˜$Kš
œ$˜$Kš
œ$˜$Kš
œ˜—K™š‘œ™"š‘
œžœžœ™'šžœžœ
žœž™Kš
œ"™"Kšžœ
™—šžœžœ
žœž™Kš
œ'™'Kš
œ#™#Kšžœ
™—šžœžœ
žœž™Kš
œ'™'Kšžœ
™—K™—Kš
œ™Kš
œ™K™Kš
œ"™"Kš
œ$™$Kš
œ$™$Kš
œ$™$Kš
œ™Kš
œ™—K˜š‘œ˜"Kš‘
œžœ€œ€
œ˜,Kš‘œžœ€œ€œ˜<š‘œžœ$žœ
žœ(žœžœ˜wKš
œ,˜,K˜—š‘œžœ˜%Kšžœ	žœ	žœ	žœ	žœ
žœ
žœ
˜GKšœ
€œ
˜
Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.K™Kš€œ€$˜.Kšœ
€œ
˜
K˜—š‘œžœ˜%Kšžœ	žœ	žœ	žœ	žœ
žœ
˜:Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.Kš€œ€$˜.K™Kš€œ€$˜.Kšœ
€œ
˜
K˜—Kš
œ˜Kš
œ ˜ š
œJ™JKšœ
€œ
˜
Kš€œ€&œ€Πfk€˜>Kšœ
€œ
˜
Kš€œ€&œ€₯€˜?—šœΟbœ
™Kšœ
€œ
˜
Kš€œ€&ž€₯€˜?Kšœ
€œ
˜
Kš€œ€&ž€₯€˜>Kšœ
€œ
˜
Kš€œ€&œ€₯€˜AKšœ
€œ
˜
Kš€œ€&œ€₯€˜B—™EKšœ
€œ
˜
Kš€œ€&ž€₯€˜<Kšœ
€œ
˜
Kš€œ€&ž€₯€˜=Kšœ
€œ
˜
Kš€œ€&ž€₯€˜<Kšœ
€œ
˜
Kš€œ€&ž€₯€˜=—šœžœ™Kšœ
€œ
˜
Kš€œ€&ž€₯€˜<Kš€œ€&ž€₯€˜=K˜Kš€œ€&ž€₯€˜<Kš€œ€&ž€₯€˜=K˜Kš€œ€&ž€₯€˜<Kš€œ€&ž€₯€˜=—šœ"¦œ
™)Kš€2ž€₯€Πcf
˜GKš€2ž€₯€§
˜KKš€2ž€₯€§
˜GKš€2ž€₯€§˜FKš€2œ€₯€§
˜KKš€2œ€₯€§
˜MKš€2œ€₯€§
˜KKš€2œ€₯€§˜H—šœ9¦œ
™@Kšœ
€œ
˜
Kš€œ€&₯€₯€˜<Kš€œ€&₯€₯€˜<Kš€œ€&₯€₯€˜<Kš€œ€&₯€₯€˜=Kš€œ€&₯€₯€˜=Kš€œ€&₯€₯€˜=K˜—K˜šœ1¦œ
™8Kš
€3˜3Kš
€3˜3Kš
€3˜3Kš
€3˜3—šœ¦œ
™Kš
€.˜.Kš
€0˜0Kš
€0˜0—šœ¦œ
™Kšœ€
œ€˜Kšœ€
œ€˜Kšœ€
œ€˜Kšœ€
œ€˜Kšœ€
œ€˜—šœ¦œ
™Kšœ€
œ€˜Kšœ€
œ€˜Kšœ€
œ€˜Kšœ€
œ€˜—šœ¦œ
™Kš€2œ€₯€˜@Kš€2œ	€₯€˜C—Kš
œ˜—š‘œ˜!š‘œžœžœ
žœ
žœžœ˜RKš
œ2˜2K˜—Kš
œ˜šœ%¦œ
™,šžœžœ
žœ	ž˜Kš
œF˜FKšžœ
˜——šœ-¦œ
™4šžœžœ
žœ	ž˜Kš
œE˜EKšžœ
˜——šœ ¦œ
™'šžœžœ
žœ	ž˜Kšœ=žœžœ˜\Kšžœ
˜——šœ¦œ
™Kšœ"€
œžœ˜OKšœ"€
œžœ˜PKšœ"€
œžœ˜QKšœJžœ˜PKšœ"€
œžœ˜Q—Kš
œ˜K˜—š‘œ˜!Kš
œ˜K˜—K˜Kšœžœžœžœ
˜)Kš
œ)˜)Kš
œ4˜4Kš
œ-˜-Kš
œ-˜-Kš
œ+˜+Kšœžœ#˜-Kš
œ.˜.Kš
œ-˜-K˜Kš
œ1˜1Kš
œ<˜<Kš
œ3˜3Kš
œ3˜3Kš
œ1˜1—K˜Kšžœ
˜K˜K˜K˜š‘	œžœ
žœ˜"Kšœ
žœ
˜K˜Kšœžœ ˜%Kšœžœ
˜Jš
œ˜K˜Kšœžœ ˜&Kšœžœ
˜Jš
œ˜K˜Kšœžœ $˜7Kšœžœ
˜Kš
œ˜Kš
œ˜Jš
œ˜K˜Kšœžœ ˜$Kšœžœ
˜Kš
œ˜Kšœ
žœ
˜Kšœ
žœ
˜Kšœ
žœ
˜Kš
œ˜Jš
œ˜K˜—K˜—…—AF]Δ