DIRECTORY Core, Ports; EU: CEDAR DEFINITIONS = BEGIN CreateEU: PUBLIC PROC [typeData: REF EUTypeData _ NIL, fullEU: BOOL _ FALSE, useCkPt: BOOL _ FALSE] RETURNS [cellType: Core.CellType]; EUState: TYPE = REF EUStateRec; EUStateRec: TYPE = RECORD[ data: REF EUTypeData _ NIL, Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, VRef, DPRejectB, DPData, -- 32 bits KBus, -- 32 bits EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, -- 4 bits Dragon.ALUOps EUCondSel2AB, -- 4 bits Dragon.CondSelects EUCondition2B, DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT _ LAST[NAT], reg: ARRAY PipeRange OF CARD _ ALL[0], shRegA, shRegB: CARD _ 0, -- the data part of the DBus shift register op, dStateAd: NAT _ 0, -- the remainder of the shift register prevDShift, prevDExecute: Ports.Level _ X, -- the DShift clock is edge-triggered carryAB, carryBA: BOOL _ FALSE, conditionBA: BOOL _ FALSE, -- needed during A to update carryAB rejectBA: BOOL _ FALSE, -- a copy of DPRejectB stable during PhA readPBusBA: BOOL _ FALSE, -- a copy of EURdFromPBus3AB stable during the next PhA size: NAT _ nRegs, ram: ARRAY [0..nRegs) OF CARD ]; PipeRange: TYPE = [left..dataIn]; -- states left: NAT = 0; right: NAT = 1; st2A: NAT = 2; st2B: NAT = 3; st3A: NAT = 4; kReg: NAT = 5; field: NAT = 6; r2B: NAT = 7; -- rBus r3A: NAT = 8; r3B: NAT = 9; -- cBus dataIn: NAT = 10; -- cBus EUTypeData: TYPE = RECORD [ data: REF ANY, storeNoted: BOOL, noteStore: NoteRegStoreProc _ NIL ]; NoteRegStoreProc: TYPE = PROC [ data: REF ANY, reg: [0..256), value: CARD ]; nRegs: NAT = 160; END. nEU.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Louis Monier June 2, 1986 3:52:58 pm PDT McCreight, April 10, 1986 12:13:37 pm PST Barth, April 19, 1986 5:23:49 pm PST Bertrand Serlet June 7, 1986 7:10:28 pm PDT Last Edited by: Louis Monier November 17, 1986 1:53:04 am PST -- kitchen sink -- ports indexes -- Phase-multiplexed on KBus aAdr [0..7] bAdr [8..15] cAdr [16..23] EUSt3AisCBus2BA [24] EUAluLeftSrc1BA [25..26] EUAluRightSrc1BA [27..29] EUStore2ASrc1BA [30..31] -- registers -- a few bits of state -- register file ram: SEQUENCE size: NAT OF CARD -- pipeline registers indexes Κb˜šΟkœ™Icodešœ Οmœ1™