C0 W0 17 0 W1 0 2 A0 CoreName r R0 "phB" A1 Side a A2 right W2 0 2 A0 r R1 "readPBus3AB" A1 a A3 left W3 0 2 A0 r R2 "condition" A1 a A3 W4 3 1 A0 r R3 "opL" W5 0 1 A1 a A2 W6 0 1 A1 a A2 W7 0 1 A1 a A2 W8 3 1 A0 r R4 "res" W9 0 1 A1 a A2 WA 0 1 A1 a A2 WB 0 1 A1 a A2 WC 5 1 A0 r R5 "selCarry" WD 0 1 A1 a A2 WE 0 1 A1 a A2 WF 0 1 A1 a A2 W10 0 1 A1 a A2 W11 0 1 A1 a A2 W12 0 2 A0 r R6 "zero" A1 a A2 W13 0 2 A0 r R7 "dpRejectB" A1 a A3 W14 4 1 A0 r R8 "condSel" W15 0 1 A1 a A3 W16 0 1 A1 a A3 W17 0 1 A1 a A3 W18 0 1 A1 a A3 W19 3 1 A0 r R9 "opR" W1A 0 1 A1 a A2 W1B 0 1 A1 a A2 W1C 0 1 A1 a A2 W1D 0 2 A0 r RA "phA" A1 a A2 W1E 0 2 A0 r RB "carryOut" A1 a A2 W1F 0 2 A0 r RC "reject" A1 a A4 bottom W20 0 2 A0 r RD "readPBus" A1 a A4 W21 0 2 A0 r RE "carryIn" A1 a A2 W22 0 1 A0 r RF "Gnd" W23 0 1 A0 r R10 "Vdd" 2 A0 r R11 "SCControl" A5 Layout a A6 SC R12 "Record" 5 W24 18 0 W25 0 0 W20 W14 W12 W1F W1D W1 W1E W2 W8 WC W13 W19 W4 W3 W21 W23 W22 W26 5 0 W23 W22 W1E WF W25 1 A0 r R13 "/0(Xor2)*2" C1 W0 5 0 W1 0 2 A0 r R10 A7 PortData l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R14 "I-A" A7 l agg n 0 W4 0 2 A0 r R15 "I-B" A7 l agg n 0 W5 0 2 A0 r R16 "X" A7 l agg d 0 3 A0 r R17 "Xor2" A8 RoseBehave r R17 A9 CoreCutLabel lor 1 R18 "Logic" R19 "LibCell" R1A "CMOSB" R1B "xor2" W27 5 0 W23 W22 W2 W20 W1 1 A0 r R1C "/1(DL)*2" C2 W0 5 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R1D "D" A7 l agg n 0 W4 0 2 A0 r R1E "Q" A7 l agg d 0 W5 0 2 A0 r R1F "S" A7 l agg n 0 3 A0 r R20 "DL" A8 r R20 A9 lor 1 R18 R19 R1A R21 "dLatch" W28 9 0 W3 W1 W1F W21 W1D W25 WC W22 W23 0 C3 W0 9 0 W1 0 1 A0 r R2 W2 0 1 A0 r R0 W3 0 1 A0 r RC W4 0 1 A0 r RE W5 0 1 A0 r RA W6 0 1 A0 r RB W7 5 1 A0 r R5 W8 0 1 A0 r R22 "CBAisZero" W9 0 1 A0 r R23 "CBAisCout" WA 0 0 WB 0 1 A0 r R24 "CINisCAB" WC 0 1 A0 r R25 "invertCin" WD 0 1 A0 r RF WE 0 1 A0 r R10 1 A0 r R26 "carry" R12 14 WF 19 0 W7 W10 0 1 A0 r R27 "carryBA" W6 W3 W11 0 0 W12 0 1 A0 r R28 "carryAB" W13 0 0 W14 0 0 W15 0 0 W16 0 0 W1 W2 W17 0 0 W18 0 0 W19 0 0 W5 W4 WE WD W1A 5 0 WE WD W14 W10 W2 1 A0 r R29 "/2(carry)/0(DL)*2" C2 W1B 5 0 W8 W14 W19 WD WE 0 C4 W0 5 0 W1 0 1 A0 r R15 W2 0 1 A0 r R16 W3 0 1 A0 r R14 W4 0 1 A0 r RF W5 0 1 A0 r R10 1 A0 r R2A "nor2" R12 1 W6 4 0 W7 2 2 A0 r R2B "I" AA GivenName a AA W3 W1 W2 W5 W4 W8 4 0 W5 W4 W7 W2 0 C5 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 2 2 A0 r R2B A7 ls agg n 0 W4 0 0 W5 0 0 W6 0 2 A0 r R16 A7 l agg d 0 3 A0 r R2C "NormalizedNor2" A8 r R2D "Nor" A9 lor 1 R18 R12 1 W0 W7 5 0 W1 W2 W4 W5 W6 0 C6 W0 5 0 W1 0 1 A0 r R10 W2 0 1 A0 r RF W3 0 1 A0 r R14 W4 0 1 A0 r R15 W5 0 1 A0 r R16 3 A0 r R2E "Nor2" A8 r R2E A9 lor 1 R18 R19 R1A R2A W1C 7 0 WE WD W12 W16 W6 W9 W19 1 A0 r R2F "/2(carry)/2(A22o2i)*2" C7 W0 7 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R30 "A" A7 l agg n 0 W4 0 2 A0 r R31 "B" A7 l agg n 0 W5 0 2 A0 r R32 "C" A7 l agg n 0 W6 0 2 A0 r R1D A7 l agg n 0 W7 0 2 A0 r R16 A7 l agg d 0 3 A0 r R33 "A22o2i" A8 r R33 A9 lor 1 R18 R19 R1A R34 "a22o2i" W1D 4 0 WE WD W18 W4 1 A0 r R35 "/2(carry)/3(Inv)*2" C8 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R2B A7 l agg n 0 W4 0 2 A0 r R16 A7 l agg d 0 3 A0 r R36 "Inv" A8 r R36 A9 lor 1 R18 R19 R1A R37 "inv" W1E 4 0 WE WD W18 W4 1 A0 r R38 "/2(carry)/4(Inv)*2" C8 W1F 4 0 WE WD W18 W4 1 A0 r R39 "/2(carry)/5(Inv)*2" C8 W20 4 0 WE WD W18 W4 1 A0 r R3A "/2(carry)/6(Inv)*2" C8 W21 5 0 W9 W16 W8 WD WE 0 C4 W22 5 0 WE WD W13 WC W18 1 A0 r R3B "/2(carry)/8(Xor2)*2" C1 W23 5 0 WE WD W17 W12 W5 1 A0 r R3C "/2(carry)/9(DL)*2" C2 W24 5 0 WB W12 W13 WD WE 0 C9 W0 5 0 W1 0 1 A0 r R15 W2 0 1 A0 r R14 W3 0 1 A0 r R16 W4 0 1 A0 r RF W5 0 1 A0 r R10 1 A0 r R3D "nand2" R12 1 W6 4 0 W7 2 2 A0 r R2B AA a AA W2 W1 W3 W5 W4 W8 4 0 W5 W4 W7 W3 0 CA W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 2 2 A0 r R2B A7 ls agg n 0 W4 0 0 W5 0 0 W6 0 2 A0 r R16 A7 l agg d 0 3 A0 r R3E "NormalizedNand2" A8 r R3F "Nand" A9 lor 1 R18 R12 1 W0 W7 5 0 W1 W2 W4 W5 W6 0 CB W0 5 0 W1 0 1 A0 r R10 W2 0 1 A0 r RF W3 0 1 A0 r R14 W4 0 1 A0 r R15 W5 0 1 A0 r R16 3 A0 r R40 "Nand2" A8 r R40 A9 lor 1 R18 R19 R1A R3D W25 4 0 WE WD W15 W17 1 A0 r R41 "/2(carry)/11(Inv)*2" C8 W26 6 0 W12 W10 W11 W15 WD WE 0 CC W0 6 0 W1 0 1 A0 r R30 W2 0 1 A0 r R31 W3 0 1 A0 r R42 "selA" W4 0 1 A0 r R43 "nOut" W5 0 1 A0 r RF W6 0 1 A0 r R10 1 A0 r R44 "invMux2" R12 2 W7 7 0 W1 W2 W8 0 0 W3 W4 W6 W5 W9 7 0 W6 W5 W1 W8 W3 W2 W4 1 A0 r R45 "/2(carry)/12(invMux2)/0(A22o2i)*2" CD W0 7 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R30 A7 l agg n 0 W4 0 2 A0 r R31 A7 l agg n 0 W5 0 2 A0 r R32 A7 l agg n 0 W6 0 2 A0 r R1D A7 l agg n 0 W7 0 2 A0 r R16 A7 l agg d 0 3 A0 r R33 A8 r R33 A9 lor 1 R18 R19 R1A R34 WA 4 0 W6 W5 W3 W8 1 A0 r R46 "/2(carry)/12(invMux2)/1(Inv)*2" CE W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R2B A7 l agg n 0 W4 0 2 A0 r R16 A7 l agg d 0 3 A0 r R36 A8 r R36 A9 lor 1 R18 R19 R1A R37 W27 5 0 W1 W11 W3 WD WE 0 C4 W29 5 0 W23 W22 W13 W1F W1 1 A0 r R47 "/3(DL)*2" C2 W2A 10 0 W1 W14 W8 W12 W19 W25 W3 W4 W23 W22 0 CF W0 10 0 W1 0 1 A0 r R0 W2 4 1 A0 r R8 W3 0 0 W4 0 1 A0 r R48 "invertCond" W5 0 0 W6 0 0 W7 3 1 A0 r R4 W8 0 1 A0 r R49 "res0" W9 0 0 WA 0 0 WB 0 1 A0 r R6 WC 3 1 A0 r R9 WD 0 0 WE 0 0 WF 0 0 W10 0 1 A0 r RB W11 0 1 A0 r R2 W12 3 1 A0 r R3 W13 0 0 W14 0 0 W15 0 0 W16 0 1 A0 r R10 W17 0 1 A0 r RF 1 A0 r R4A "Condition" R12 17 W18 21 0 W19 0 0 W1A 0 1 A0 r R4B "cond" W1B 0 0 W7 W1C 0 0 WC W1D 3 2 A0 r R4C "sel" AA a AA W3 W5 W6 W2 W1E 0 0 W1F 0 0 W1 W20 8 2 A0 r R4D "Input" AA a AA W17 WB W21 0 1 A0 r R4E "lz" W22 0 1 A0 r R4F "le" W23 0 1 A0 r R50 "ov" W24 0 2 A0 r R16 AA a AA W25 0 1 A0 r R51 "il" W17 W10 W12 W26 0 0 W27 0 0 W11 W28 0 0 W29 0 0 W17 W16 W2A 6 0 W19 W1B W26 W25 W17 W16 0 C10 W0 6 0 W1 0 1 A0 r R15 W2 0 1 A0 r R52 "I-C" W3 0 1 A0 r R14 W4 0 1 A0 r R16 W5 0 1 A0 r RF W6 0 1 A0 r R10 1 A0 r R53 "nand3" R12 1 W7 4 0 W8 3 2 A0 r R2B AA a AA W3 W1 W2 W4 W6 W5 W9 4 0 W6 W5 W8 W4 0 C11 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 3 2 A0 r R2B A7 ls agg n 0 W4 0 0 W5 0 0 W6 0 0 W7 0 2 A0 r R16 A7 l agg d 0 3 A0 r R54 "NormalizedNand3" A8 r R3F A9 lor 1 R18 R12 1 W0 W8 6 0 W1 W2 W4 W5 W6 W7 0 C12 W0 6 0 W1 0 1 A0 r R10 W2 0 1 A0 r RF W3 0 1 A0 r R14 W4 0 1 A0 r R15 W5 0 1 A0 r R52 W6 0 1 A0 r R16 3 A0 r R55 "Nand3" A8 r R55 A9 lor 1 R18 R19 R1A R53 W2B 4 0 W16 W17 W1F W11 1 A0 r R56 "/4(Condition)/1(Inv)*2" C13 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R2B A7 l agg n 0 W4 0 2 A0 r R16 A7 l agg d 0 3 A0 r R36 A8 r R36 A9 lor 1 R18 R19 R1A R37 W2C 4 0 W16 W17 W1F W11 1 A0 r R57 "/4(Condition)/2(Inv)*2" C13 W2D 5 0 W16 W17 W8 W21 W23 1 A0 r R58 "/4(Condition)/3(Xor2)*2" C1 W2E 4 0 W16 W17 W1F W11 1 A0 r R59 "/4(Condition)/4(Inv)*2" C13 W2F 4 0 W7 W26 W16 W17 0 C14 W0 4 0 W1 3 1 A0 r R5A "in" W2 0 0 W3 0 0 W4 0 0 W5 0 1 A0 r R5B "out" W6 0 1 A0 r R10 W7 0 1 A0 r RF 1 A0 r R5C "IsLisp" R12 3 W8 6 0 W5 W9 0 0 W1 WA 0 0 W7 W6 WB 5 0 WA W9 W5 W7 W6 0 C9 WC 6 0 W3 W4 W2 W9 W7 W6 0 C10 WD 6 0 WA W2 W3 W4 W7 W6 0 C15 W0 6 0 W1 0 1 A0 r R16 W2 0 1 A0 r R14 W3 0 1 A0 r R15 W4 0 1 A0 r R52 W5 0 1 A0 r RF W6 0 1 A0 r R10 1 A0 r R5D "or3" R12 1 W7 4 0 W1 W8 3 2 A0 r R2B AA a AA W2 W3 W4 W6 W5 W9 4 0 W6 W5 W8 W1 0 C16 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 3 2 A0 r R2B A7 ls agg n 0 W4 0 0 W5 0 0 W6 0 0 W7 0 2 A0 r R16 A7 l agg d 0 3 A0 r R5E "NormalizedOr3" A8 r R5F "Or" A9 lor 1 R18 R12 1 W0 W8 6 0 W1 W2 W4 W5 W6 W7 0 C17 W0 6 0 W1 0 1 A0 r R10 W2 0 1 A0 r RF W3 0 1 A0 r R14 W4 0 1 A0 r R15 W5 0 1 A0 r R52 W6 0 1 A0 r R16 3 A0 r R60 "Or3" A8 r R60 A9 lor 1 R18 R19 R1A R5D W30 4 0 W16 W17 W1F W11 1 A0 r R61 "/4(Condition)/6(Inv)*2" C13 W31 5 0 WB W21 W22 W17 W16 0 C18 W0 5 0 W1 0 1 A0 r R15 W2 0 1 A0 r R14 W3 0 1 A0 r R16 W4 0 1 A0 r RF W5 0 1 A0 r R10 1 A0 r R62 "or2" R12 1 W6 4 0 W7 2 2 A0 r R2B AA a AA W2 W1 W3 W5 W4 W8 4 0 W5 W4 W7 W3 0 C19 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 2 2 A0 r R2B A7 ls agg n 0 W4 0 0 W5 0 0 W6 0 2 A0 r R16 A7 l agg d 0 3 A0 r R63 "NormalizedOr2" A8 r R5F A9 lor 1 R18 R12 1 W0 W7 5 0 W1 W2 W4 W5 W6 0 C1A W0 5 0 W1 0 1 A0 r R10 W2 0 1 A0 r RF W3 0 1 A0 r R14 W4 0 1 A0 r R15 W5 0 1 A0 r R16 3 A0 r R64 "Or2" A8 r R64 A9 lor 1 R18 R19 R1A R62 W32 4 0 W16 W17 W28 W1F 1 A0 r R65 "/4(Condition)/8(Inv)*2" C13 W33 4 0 W12 W19 W16 W17 0 C14 W34 5 0 W16 W17 W29 W28 W1 1 A0 r R66 "/4(Condition)/10(DL)*2" C2 W35 4 0 WC W1B W16 W17 0 C14 W36 5 0 W16 W17 W1A W4 W29 1 A0 r R67 "/4(Condition)/12(Xor2)*2" C1 W37 5 0 W16 W17 W1E W10 W21 1 A0 r R68 "/4(Condition)/13(Xor2)*2" C1 W38 5 0 W16 W17 WD W13 W1E 1 A0 r R69 "/4(Condition)/14(Xor2)*2" C1 W39 5 0 W20 W1A W1D W16 W17 0 C1B W0 5 0 W1 8 1 A0 r R4D W2 0 0 W3 0 0 W4 0 0 W5 0 0 W6 0 0 W7 0 0 W8 0 0 W9 0 0 WA 0 1 A0 r R6A "Output" WB 3 1 A0 r R4C WC 0 0 WD 0 0 WE 0 0 WF 0 1 A0 r R10 W10 0 1 A0 r RF 1 A0 r R6B "decoder3" R12 23 W11 20 0 W12 0 0 WA W13 0 0 WB W14 0 0 W15 0 0 W16 0 0 W17 0 0 W18 0 0 W19 0 0 W1A 0 0 W1 W1B 0 0 W1C 0 0 W1D 0 0 W1E 0 0 W1F 0 0 W20 0 0 W10 WF W21 5 0 W9 W15 W1E W10 WF 0 C1C W0 5 0 W1 0 1 A0 r R2B W2 0 1 A0 r R16 W3 0 1 A0 r R6C "EN" W4 0 1 A0 r RF W5 0 1 A0 r R10 1 A0 r R6D "3BufferI" R12 2 W6 6 0 W3 W1 W7 0 0 W2 W5 W4 W8 4 0 W5 W4 W3 W7 1 A0 r R6E "/4(Condition)/15(decoder3)/14(3BufferI)//4(Condition)/15(decoder3)/12(3BufferI)//4(Condition)/15(decoder3)/9(3BufferI)//4(Condition)/15(decoder3)/7(3BufferI)//4(Condition)/15(decoder3)/5(3BufferI)//4(Condition)/15(decoder3)/3(3BufferI)//4(Condition)/15(decoder3)/2(3BufferI)//4(Condition)/15(decoder3)/0(3BufferI)/0(Inv)*2*2*2*2*2*2*2*2" C1D W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R2B A7 l agg n 0 W4 0 2 A0 r R16 A7 l agg d 0 3 A0 r R36 A8 r R36 A9 lor 1 R18 R19 R1A R37 W9 6 0 W5 W4 W1 W2 W3 W7 1 A0 r R6F "/4(Condition)/15(decoder3)/14(3BufferI)//4(Condition)/15(decoder3)/12(3BufferI)//4(Condition)/15(decoder3)/9(3BufferI)//4(Condition)/15(decoder3)/7(3BufferI)//4(Condition)/15(decoder3)/5(3BufferI)//4(Condition)/15(decoder3)/3(3BufferI)//4(Condition)/15(decoder3)/2(3BufferI)//4(Condition)/15(decoder3)/0(3BufferI)/1(TstDriver)*2*2*2*2*2*2*2*2" C1E W0 6 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R2B A7 l agg n 0 W4 0 2 A0 r R16 A7 l agg n 0 W5 0 2 A0 r R6C A7 l agg n 0 W6 0 2 A0 r R70 "NEN" A7 l agg n 0 3 A0 r R71 "TstDriver" A8 r R71 A9 lor 1 R18 R19 R1A R72 "tstDriver" W22 4 0 WF W10 W15 WA 1 A0 r R73 "/4(Condition)/15(decoder3)/1(Inv)*2" C1F W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 0 2 A0 r R2B A7 l agg n 0 W4 0 2 A0 r R16 A7 l agg d 0 3 A0 r R36 A8 r R36 A9 lor 1 R18 R19 R1A R37 W23 5 0 W8 W15 W19 W10 WF 0 C1C W24 5 0 W7 W15 W1D W10 WF 0 C1C W25 6 0 W18 W1E W1F W14 W10 WF 0 C20 W0 6 0 W1 0 1 A0 r R15 W2 0 1 A0 r R16 W3 0 1 A0 r R52 W4 0 1 A0 r R14 W5 0 1 A0 r RF W6 0 1 A0 r R10 1 A0 r R74 "nor3" R12 1 W7 4 0 W2 W8 3 2 A0 r R2B AA a AA W4 W1 W3 W6 W5 W9 4 0 W6 W5 W8 W2 0 C21 W0 4 0 W1 0 2 A0 r R10 A7 l agg n 0 W2 0 2 A0 r RF A7 l agg n 0 W3 3 2 A0 r R2B A7 ls agg n 0 W4 0 0 W5 0 0 W6 0 0 W7 0 2 A0 r R16 A7 l agg d 0 3 A0 r R75 "NormalizedNor3" A8 r R2D A9 lor 1 R18 R12 1 W0 W8 6 0 W1 W2 W4 W5 W6 W7 0 C22 W0 6 0 W1 0 1 A0 r R10 W2 0 1 A0 r RF W3 0 1 A0 r R14 W4 0 1 A0 r R15 W5 0 1 A0 r R52 W6 0 1 A0 r R16 3 A0 r R76 "Nor3" A8 r R76 A9 lor 1 R18 R19 R1A R74 W26 5 0 W6 W15 W1B W10 WF 0 C1C W27 6 0 W18 W19 W1F W16 W10 WF 0 C20 W28 5 0 W5 W15 W1A W10 WF 0 C1C W29 6 0 W20 W1D W1F W14 W10 WF 0 C20 W2A 5 0 W4 W15 W17 W10 WF 0 C1C W2B 6 0 W20 W1B W1F W16 W10 WF 0 C20 W2C 6 0 W18 W1A W13 W14 W10 WF 0 C20 W2D 5 0 W3 W15 W1C W10 WF 0 C1C W2E 6 0 W18 W17 W13 W16 W10 WF 0 C20 W2F 5 0 W2 W15 W12 W10 WF 0 C1C W30 6 0 W20 W1C W13 W14 W10 WF 0 C20 W31 6 0 W20 W12 W13 W16 W10 WF 0 C20 W32 4 0 WF W10 W14 W16 1 A0 r R77 "/4(Condition)/15(decoder3)/17(Inv)*2" C1F W33 4 0 WF W10 W18 W20 1 A0 r R78 "/4(Condition)/15(decoder3)/18(Inv)*2" C1F W34 4 0 WF W10 W1F W13 1 A0 r R79 "/4(Condition)/15(decoder3)/19(Inv)*2" C1F W35 4 0 WF W10 WE W14 1 A0 r R7A "/4(Condition)/15(decoder3)/20(Inv)*2" C1F W36 4 0 WF W10 WD W18 1 A0 r R7B "/4(Condition)/15(decoder3)/21(Inv)*2" C1F W37 4 0 WF W10 WC W1F 1 A0 r R7C "/4(Condition)/15(decoder3)/22(Inv)*2" C1F W3A 4 0 W16 W17 W10 W24 1 A0 r R7D "/4(Condition)/16(Inv)*2" C1F