[Indigo]<Dragon>EU3Saved>EUUtils.mesa!1

EUUtils.mesa

Last Edited by: Louis Monier November 4, 1986 1:08:03 pm PST

DIRECTORY CD, CoreCreate, Dragon, Ports, Rope;

EUUtils: CEDAR DEFINITIONS = BEGIN

OPEN CoreCreate;

eu2Design, alpsDesign: READONLY CD.Design;

Extract: PROC [name: Rope.ROPE] RETURNS [cellType: CellType];

AlpsExtract: PROC [name: Rope.ROPE] RETURNS [cellType: CellType];

-- uses a global table of [name, cellType]

Store: PUBLIC PROC [name: ROPE, ct: CellType];

Fetch: PUBLIC PROC [name: ROPE] RETURNS [CellType];

Delete: PUBLIC PROC [name: ROPE];

Write: PUBLIC PROC;

Read: PUBLIC PROC [name: ROPE, withLayout: BOOL ← FALSE];

-- The RAM

nRows: NAT; -- one row is a Quadword; 40=real EU; 2=small EU

nbWords: NAT;

stackAdr, junkAdr, fieldAdr, marAdr, constAdr, IFUAdr, bogusAdr: NAT;

-- ALU

Carry: TYPE = {zero, one, comp, ncomp, prev, nprev};

ALUOpcode: TYPE = {add, and, or, xor};

ALUOpRec: TYPE = RECORD[

op: ALUOpcode,

invertB: BOOL ← FALSE,

cIn, cOut: Carry ← prev

];

aluOps: ARRAY Dragon.ALUOps OF ALUOpRec;

-- Buses

BusRange: TYPE = [left..pIn];

Bus: TYPE = REF BusRec; -- a bus in the datapath

BusRec: TYPE = RECORD[

name: ROPE,

trackPosX: [0..maxBuses),

top: SourceRange,

bottom: SourceRange

];

buses: READONLY ARRAY BusRange OF Bus; -- all buses in the datapath

left: NAT = 0;

right: NAT = 1;

st2A: NAT = 2;

st2B: NAT = 3;

st3A: NAT = 4;

kReg: NAT = 5;

field: NAT = 6;

r2B: NAT = 7; -- rBus

r3A: NAT = 8;

cBus: NAT = 9;

pDriver: NAT = 10;

ramA: NAT = 11;

ramB: NAT = 12;

ifuIn: NAT = 13; -- kBus

aluOut: NAT = 14;

fuOut: NAT = 15;

pIn: NAT = 16;

-- Registers

PipeRange: TYPE = [leftRow..dataInRow]; -- states

SourceRange: TYPE = [leftRow..bottomRow];

maxSel: NAT = 5;

maxBuses: NAT = 6;

InputSels: TYPE = ARRAY [0..maxSel) OF BusRange;

Source: TYPE = REF SourceRec; -- a register, or other block in the datapath

SourceRec: TYPE = RECORD[ -- a register, or other block in the datapath

name: ROPE ← NIL,

position: NAT, -- 0 is on top; only relative position imports

nameSel: ROPE ← NIL,

sizeSel: NAT ← 0,

tristate: BOOL ← FALSE,

output: BusRange ← 0, -- index of bus

inputs: InputSels ← [0, 0, 0, 0, 0] -- indexes of buses

];

sources: READONLY ARRAY SourceRange OF Source;

-- pipeline registers

leftRow: NAT = 0;

rightRow: NAT = 1;

st2ARow: NAT = 2;

st2BRow: NAT = 3;

st3ARow: NAT = 4;

kRegRow: NAT = 5;

fieldRow: NAT = 6;

r2BRow: NAT = 7; -- rBus

r3ARow: NAT = 8;

r3BRow: NAT = 9; -- cBus

dataInRow: NAT = 10; -- cBus

-- other sources for buses, but not registers

ramRow: NAT = 11;

aluRow: NAT = 12;

fuRow: NAT = 13;

pDriverRow: NAT = 14;

ifuInRow: NAT = 15; -- kBus

bottomRow: NAT = 16; -- toPBus and fromPBus

CSeqX: PROC [name: ROPE, ct: CellType, count: NAT, wrs: LIST OF WR] RETURNS [CellType];

CSeqY: PROC [name: ROPE, ct: CellType, count: NAT, wrs: LIST OF WR] RETURNS [CellType];

InitLeafPorts: PUBLIC PROC [public: Wire, initDrive: Ports.Drive];

GenWiresForBonnie: PROC RETURNS [Wire];

GenWiresForOnion: PROC RETURNS [Wire];

GenRegSelWire: PROC [reg: PipeRange] RETURNS [Wire];

END.