EUALUImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier June 19, 1986 4:45:22 pm PDT
Last Edited by: Louis Monier November 15, 1986 0:02:20 am PST
DIRECTORY CoreCreate, EUInner, EUUtils;
EUALUImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, EUUtils
EXPORTS EUInner =
BEGIN OPEN CoreCreate, EUInner;
-- Buses: (left, right, aluOut, st2A, r2B, cBus)[0..32), Vdd, Gnd
-- From ctrl: carryIn, op[0..5)
-- To ctrl: p0to31, carry[31], aluOut[0..8), left[0..3), right[0..3), right[19..32)
-- Coming out of this channel:
p0to31, carry[31], carryOut, aluOut[0..8), left[0..3), right[0..3), right[19..32)
CreateALU:
PUBLIC
PROC []
RETURNS [ct: CellType] = {
ct ← EUUtils.Fetch["ALU"];
IF ct=
NIL
THEN {
ct ← EUUtils.Extract["ALU.sch"];
EUUtils.Store["ALU", ct];
};
};
-- Function Blocks: generate P and G, combine C to produce aluOut
-- (left, right, aluOut, st2A, r2B, cBus, G, P, carry)[0..32), op[0..5), Vdd, Gnd
CreateFunctionBlock:
PUBLIC PROC
RETURNS [cellType: CellType] = {
cellType ← EUUtils.CSeqX["FunctionBlock", EUUtils.Extract["ALUFnBlock.sch"], 32,
LIST["left", "right", "aluOut", "st2A", "r2B", "cBus", "G", "P", "carry"]];
};
CreateCarryProp:
PUBLIC
PROC
RETURNS [cellType: CellType] = {
cellType ← EUUtils.CSeqX["CarryProp", EUUtils.Extract["ALUCP.sch"], 32,
LIST["Gleft", "G", "Gright", "Pleft", "P", "Pright", "C", "Cin", "left", "right", "st2A", "r2B", "cBus"]];
};
-- Generates the DAG which connects L, M, R and B as needed to wire P and G for the ALU.
Tree:
PUBLIC
PROC []
RETURNS [tree: Wire] ~ {
left: Wire ← Seq[size: 32];
middle: Wire ← Seq[size: 32];
right: Wire ← Seq[size: 32];
bottom: Wire ← Seq[size: 32];
Connect:
PROC [root, deltaSon:
NAT]
RETURNS [wire: Wire] ~ {
IF deltaSon=0 THEN {left[root] ← bottom[root-1]; right[root] ← bottom[root]}
ELSE {
left[root] ← Connect[root-deltaSon, deltaSon/2];
right[root] ← Connect[root+deltaSon, deltaSon/2];};
RETURN[middle[root]];
};
[] ← Connect[16, 8];
right[0] ← middle[16];
tree ← Wires[left, middle, right, bottom];
};
SmallTree:
PROC [size:
NAT]
RETURNS [tree: Wire] ~ {
left: Wire ← Seq[size: size];
middle: Wire ← Seq[size: size];
right: Wire ← Seq[size: size];
bottom: Wire ← Seq[size: size];
Connect:
PROC [root, deltaSon:
NAT]
RETURNS [wire: Wire] ~ {
IF deltaSon=0 THEN {left[root] ← bottom[root-1]; right[root] ← bottom[root]}
ELSE {
left[root] ← Connect[root-deltaSon, deltaSon/2];
right[root] ← Connect[root+deltaSon, deltaSon/2];};
RETURN[middle[root]];
};
[] ← Connect[size/2, size/4];
right[0] ← middle[size/2];
tree ← Wires[left, middle, right, bottom];
};
END.