BuildEU3.cm
Louis Monier June 18, 1986 1:45:40 am PDT
Bertrand Serlet September 20, 1986 7:28:53 pm PDT
Last Edited by: Louis Monier November 19, 1986 1:22:24 pm PST
DA.cm
Install PadFrame
run -a EUUtilsImpl
run -a EUArithImpl
run -a EURamImpl
run -a EURegsImpl
run -a EUFUImpl
run -a EUALUImpl
run -a EUControlImpl
run -a EUInnerImpl
run -a EUImpl
run -a EUSim
-- Building the chip from scratch (Core only)
← &ct ← EUInner.CreateDataPath[]
← EUUtils.Write[]
← &ct ← EUInner.CreateControl[]
← EUUtils.Write[]
← EUUtils.Read["DataPath"]
← EUUtils.Read["Control"]
← &ct ← EUInner.CreateEUInner[]
← EUUtils.Write[]
← EUUtils.Read["Inner"]
← &ct ← EU.CreateEU[fullEU: TRUE]
← EUUtils.Write[]
-- Building the chip quickly from scratch (Core only)
← &ct ← EU.CreateEU[fullEU: TRUE]
← EUUtils.Write[]
-- Reading the chip (Core only)
← EUUtils.Read["EU"]
← &ct ← EU.CreateEU[fullEU: TRUE]
← &ct ← CoreOps.Recast[&ct]
-- Transistor-level simulation
← &sim ← EUSim.ExerciseRose[&ct, LIST["Logic"]].display.simulation
-- ← &sim ← EUSim.ExerciseRose[&ct, LIST["Logic", "LogicMacro"]].display.simulation
← Rosemary.Initialize[simulation: &sim, steady: FALSE]
-- top-level simulation
← &ct ← EU.CreateEU[fullEU: FALSE]
← &sim ← EUSim.ExerciseRose[&ct, LIST["EU"]].display.simulation
← Rosemary.Initialize[simulation: &sim, steady: FALSE]
-- Layout
← &ob ← PWCore.Layout[&ct]
← PW.Draw[&ob]