DIRECTORY CoreCreate, EUInner, EUUtils; EUALUImpl: CEDAR PROGRAM IMPORTS CoreCreate, EUUtils EXPORTS EUInner = BEGIN OPEN CoreCreate, EUInner; CreateALU: PUBLIC PROC [] RETURNS [ct: CellType] = { ct _ EUUtils.Fetch["ALU"]; IF ct=NIL THEN { ct _ EUUtils.Extract["ALU.sch"]; EUUtils.Store["ALU", ct]; }; }; CreateFunctionBlock: PUBLIC PROC RETURNS [cellType: CellType] = { cellType _ EUUtils.CSeqX["FunctionBlock", EUUtils.Extract["ALUFnBlock.sch"], 32, LIST["left", "right", "aluOut", "st2A", "r2B", "cBus", "G", "P", "carry"]]; }; CreateCarryProp: PUBLIC PROC RETURNS [cellType: CellType] = { cellType _ EUUtils.CSeqX["CarryProp", EUUtils.Extract["ALUCP.sch"], 32, LIST["Gleft", "G", "Gright", "Pleft", "P", "Pright", "C", "Cin", "left", "right", "st2A", "r2B", "cBus"]]; }; Tree: PUBLIC PROC [] RETURNS [tree: Wire] ~ { left: Wire _ Seq[size: 32]; middle: Wire _ Seq[size: 32]; right: Wire _ Seq[size: 32]; bottom: Wire _ Seq[size: 32]; Connect: PROC [root, deltaSon: NAT] RETURNS [wire: Wire] ~ { IF deltaSon=0 THEN {left[root] _ bottom[root-1]; right[root] _ bottom[root]} ELSE { left[root] _ Connect[root-deltaSon, deltaSon/2]; right[root] _ Connect[root+deltaSon, deltaSon/2];}; RETURN[middle[root]]; }; [] _ Connect[16, 8]; right[0] _ middle[16]; tree _ Wires[left, middle, right, bottom]; }; SmallTree: PROC [size: NAT] RETURNS [tree: Wire] ~ { left: Wire _ Seq[size: size]; middle: Wire _ Seq[size: size]; right: Wire _ Seq[size: size]; bottom: Wire _ Seq[size: size]; Connect: PROC [root, deltaSon: NAT] RETURNS [wire: Wire] ~ { IF deltaSon=0 THEN {left[root] _ bottom[root-1]; right[root] _ bottom[root]} ELSE { left[root] _ Connect[root-deltaSon, deltaSon/2]; right[root] _ Connect[root+deltaSon, deltaSon/2];}; RETURN[middle[root]]; }; [] _ Connect[size/2, size/4]; right[0] _ middle[size/2]; tree _ Wires[left, middle, right, bottom]; }; END. ΠEUALUImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Louis Monier June 19, 1986 4:45:22 pm PDT Last Edited by: Louis Monier November 15, 1986 0:02:20 am PST -- Buses: (left, right, aluOut, st2A, r2B, cBus)[0..32), Vdd, Gnd -- From ctrl: carryIn, op[0..5) -- To ctrl: p0to31, carry[31], aluOut[0..8), left[0..3), right[0..3), right[19..32) -- Coming out of this channel: p0to31, carry[31], carryOut, aluOut[0..8), left[0..3), right[0..3), right[19..32) -- Function Blocks: generate P and G, combine C to produce aluOut -- (left, right, aluOut, st2A, r2B, cBus, G, P, carry)[0..32), op[0..5), Vdd, Gnd -- Generates the DAG which connects L, M, R and B as needed to wire P and G for the ALU. Κ±– "cedar" style˜codešœ™Kšœ Οmœ1™