MyPWCoreRouteImpl.mesa
Copyright © 1985, 1986 by Xerox Corporation. All rights reserved.
Louis Monier August 23, 1986 11:04:20 pm PDT
Last Edited by: Louis Monier September 30, 1986 1:22:29 pm PDT
DIRECTORY CD, Core, CoreClasses, CoreGeometry, CoreProperties, PWCore, PWCoreRoute, Sisyph;
MyPWCoreRouteImpl: CEDAR PROGRAM    
IMPORTS CoreGeometry, CoreProperties, PWCore, PWCoreRoute, Sisyph =
BEGIN
-- the cellType is a record with exactly two instances
SchChannel: PWCore.AttributesProc = {
[cellType: Core.CellType]
-- inX if dx>dy; I know that tis implementation is bogus; used CDBasics
DecideIfInX: PROC [i1, i2: CD.Instance] RETURNS [inX: BOOL] ~ {
dx: INTABS[i1.location.x-i2.location.x];
dy: INTABS[i1.location.y-i2.location.y];
RETURN[dx>dy];
};
CheckEachPin: CoreGeometry.EachWirePinProc = {
[wire: Core.Wire, instance: CD.Instance, min: INT, max: INT, side: CoreGeometry.Side, layer: CD.Layer] RETURNS [quit: BOOL ← FALSE]
-- remember to include only atomic wires!!!
SELECT side FROM
bottom => IF inX THEN bottomOrLeftWires ← CONS[wire, bottomOrLeftWires];
top => IF inX THEN topOrRightWires ← CONS[wire, topOrRightWires];
right => IF ~inX THEN topOrRightWires ← CONS[wire, topOrRightWires];
left => IF ~inX THEN bottomOrLeftWires ← CONS[wire, bottomOrLeftWires];
ENDCASE => ERROR;
};
channelData: PWCoreRoute.ChannelData;
inX, verticalM2, flushTopOrRight: BOOL;
prop: REF;
bottomOrLeftWires, topOrRightWires: LIST OF Core.Wire ← NIL;
decoration: CoreGeometry.Decoration ← Sisyph.mode.decoration;
data: CoreClasses.RecordCellType ← NARROW[cellType.data];
i1, i2: CD.Instance;
prop ← CoreProperties.GetCellTypeProp[cellType, $Metal2IsVertical];
verticalM2 ← IF prop#NIL THEN NARROW[prop, REF BOOL]^ ELSE TRUE;
prop ← CoreProperties.GetCellTypeProp[cellType, $FlushTopOrRight];
flushTopOrRight ← IF prop#NIL THEN NARROW[prop, REF BOOL]^ ELSE TRUE;
IF data.size#2 THEN ERROR; -- exactly two cells per channel
i1 ← CoreGeometry.GetTransf[decoration, data.instances[0]];
i2 ← CoreGeometry.GetTransf[decoration, data.instances[1]];
inX ← DecideIfInX[i1, i2];
PWCore.SortInstances[Sisyph.mode.decoration, cellType, IF inX THEN PWCore.SortInX ELSE PWCore.SortInY];
[] ← CoreGeometry.EnumerateWireSides[decoration, cellType, CheckEachPin];
channelData ← NEW[PWCoreRoute.ChannelDataRec ← [
inX: inX,
extend: TRUE, 
extendTopOrRight: flushTopOrRight,
bottomOrLeftWires: bottomOrLeftWires,
topOrRightWires: topOrRightWires,
trunkLayer: IF verticalM2 THEN "metal" ELSE "metal2",
branchLayer: IF verticalM2 THEN "metal2" ELSE "metal",
wireWidthProc: PWCoreRoute.GndAndVdd25Met2MinWidth]];
CoreProperties.PutCellTypeProp[cellType, $ChannelData, channelData];
};
layoutProc: PWCore.LayoutProc;
decorateProc: PWCore.DecorateProc;
[layoutProc, decorateProc] ← PWCore.GetLayoutAtomRegistration[$Channel];
[] ← PWCore.RegisterLayoutAtom[$CR, layoutProc, decorateProc, SchChannel];
END.