EUUtilsImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Louis Monier June 3, 1986 2:54:39 pm PDT
Bertrand Serlet August 26, 1986 1:30:17 am PDT
Last Edited by: Louis Monier November 7, 1986 0:28:32 am PST
Barth, November 24, 1986 5:26:18 pm PST
DIRECTORY BooleCore, CD, CDImports, CoreCreate, CoreIO, CoreOps, Dragon, DragOpsCross, EUUtils, HashTable, LayoutCheckpoint, Ports, PW, PWCore, Rosemary, Sisyph;
EUUtilsImpl:
CEDAR
PROGRAM
IMPORTS BooleCore, CDImports, CoreCreate, CoreOps, CoreIO, HashTable, LayoutCheckpoint, Ports, PW, PWCore, Rosemary, Sisyph
EXPORTS EUUtils =
BEGIN OPEN CoreCreate, EUUtils;
eu2Design, alpsDesign: PUBLIC CD.Design;
eu2Cx, alpsCx: Sisyph.Context;
Extract:
PUBLIC
PROC [name:
ROPE]
RETURNS [cellType: CellType] ~ {
cellType ← Sisyph.ExtractSchematicByName[name: name, cx: eu2Cx];
};
AlpsExtract:
PUBLIC
PROC [name:
ROPE]
RETURNS [cellType: CellType] ~ {
cellType ← Sisyph.ExtractSchematicByName[name: name, cx: alpsCx];
PWCore.SetGet[cellType, alpsDesign];
};
allCts: HashTable.Table ← HashTable.Create[equal: HashTable.RopeEqual, hash: HashTable.HashRope];
Fetch:
PUBLIC PROC [name:
ROPE]
RETURNS [CellType] ~ {
found: BOOL;
val: REF;
[found, val] ← HashTable.Fetch[allCts, name];
RETURN [IF ~found THEN NIL ELSE NARROW[val]];
};
Delete:
PUBLIC
PROC [name:
ROPE] ~ {
[] ← HashTable.Delete[allCts, name];
};
Store:
PUBLIC PROC [name:
ROPE, ct: CellType] ~ {
[] ← HashTable.Store[allCts, name, ct];
};
Write:
PUBLIC PROC ~ {
SaveCt: HashTable.EachPairAction ~ {[] ← CoreIO.ReportSaveCellType[NARROW[value]]};
[] ← HashTable.Pairs[allCts, SaveCt];
};
Read:
PUBLIC
PROC [name:
ROPE, withLayout:
BOOL ←
FALSE] ~ {
ct: CellType ← IF withLayout THEN LayoutCheckpoint.Retrieve[name] ELSE CoreIO.RestoreCellType[name];
Store[name, ct];
};
CSeq:
PUBLIC
PROC [inX:
BOOL, name:
ROPE, ct: CellType, count:
NAT, wrs:
LIST
OF
WR]
RETURNS [cellType: CellType] = {
cellType ← SequenceCell[name: name,
baseCell: ct, count: count,
sequencePorts: WireList[wrs]];
IF inX THEN PWCore.SetArrayX[cellType] ELSE PWCore.SetArrayY[cellType];
};
CSeqX: PUBLIC PROC [name: ROPE, ct: CellType, count: NAT, wrs: LIST OF WR] RETURNS [cellType: CellType] = {cellType ← CSeq[TRUE, name, ct, count, wrs]};
CSeqY: PUBLIC PROC [name: ROPE, ct: CellType, count: NAT, wrs: LIST OF WR] RETURNS [cellType: CellType] = {cellType ← CSeq[FALSE, name, ct, count, wrs]};
InitLeafPorts:
PUBLIC
PROC [public: Wire, initDrive: Ports.Drive] = {
-- level=b of course
InitAtomic: PROC [wire: Wire] ~ {[] ← Ports.InitPort[wire: wire, initDrive: initDrive]};
IF public.size=0 THEN InitAtomic[public] ELSE CoreOps.VisitRootAtomics[public, InitAtomic];
};
-- External wires: the golden wires, bonded by Bonnie
GenWiresForBonnie:
PUBLIC PROC
RETURNS [public: Wire] ~ {
public ← WireList[
LIST[
"Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB",
Seq["DPData", 32], "DPRejectB",
Seq["KBus", 32], "EURdFromPBus3AB", "EUWriteToPBus3AB",
Seq["EUAluOp2AB", 4], Seq["EUCondSel2AB", 4], "EUCondition2B",
"DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", Seq["DStAd", 4]
]];
[] ← Rosemary.SetFixedWire[public[CoreOps.GetWireIndex[public, "Vdd" ]], H];
[] ← Rosemary.SetFixedWire[public[CoreOps.GetWireIndex[public, "Gnd" ]], L];
[] ← Rosemary.SetFixedWire[public[CoreOps.GetWireIndex[public, "PadVdd" ]], H];
[] ← Rosemary.SetFixedWire[public[CoreOps.GetWireIndex[public, "PadGnd" ]], L];
RETURN [public];
};
GenWiresForOnion:
PUBLIC
PROC
RETURNS [Wire] = {
-- used in EUImpl
RETURN [WireList[
LIST[
"phA", "phB", "nPhA", "nPhB",
"enWrtPBusPhA", "enWrtPBusPhB", "enWrtIFUPhA", "enWrtIFUPhB", "condition",
"writePBus", "readPBus3AB", "dpRejectB", Seq["aluOp", 4], Seq["condSel", 4],
"shiftA", "shiftB", "read", "write", "shIn", "shOut", "hold", Seq["dStateAd", 4],
Seq["fromIFU", 32], Seq["toIFU", 32], Seq["toPBus", 32], Seq["fromPBus", 32],
"reject" ]]]; -- just for routing
};
GenRegSelWire:
PUBLIC
PROC [reg: PipeRange]
RETURNS [Wire] ~ {
RETURN [Seq[sources[reg].nameSel, sources[reg].sizeSel+2]]; -- sources+read+write
};
aluOps: PUBLIC ARRAY Dragon.ALUOps OF ALUOpRec;
sources: PUBLIC ARRAY SourceRange OF Source;
buses: PUBLIC ARRAY BusRange OF Bus;
-- Initialization starts here
PRtoByte: PROC[pr: DragOpsCross.ProcessorRegister] RETURNS [byte: NAT]={byte ← ORD[pr]};
Array: PROC [a, b, c, d, e: NAT ← 0] RETURNS [InputSels] ~ {RETURN[[a, b, c, d, e]]};
stackAdr: PUBLIC NAT ← PRtoByte[euStack];
junkAdr: PUBLIC NAT ← PRtoByte[euJunk];
fieldAdr: PUBLIC NAT ← PRtoByte[euField];
marAdr: PUBLIC NAT ← PRtoByte[euMAR];
constAdr: PUBLIC NAT ← PRtoByte[euConstant];
IFUAdr: PUBLIC NAT ← PRtoByte[euToKBus];
bogusAdr: PUBLIC NAT ← PRtoByte[euBogus];
nRows: PUBLIC NAT ← 40;
nbWords:
PUBLIC NAT ← 4*nRows;
-- From DragOps.tioga
aluOps[SAdd] ← [op: add, cIn: prev, cOut: zero]; -- OvFl
aluOps[SSub] ← [op: add, cIn: nprev, cOut: zero, invertB: TRUE];
aluOps[UAdd] ← [op: add, cIn: prev, cOut: comp]; -- no trap
aluOps[USub] ← [op: add, cIn: nprev, cOut: ncomp, invertB: TRUE];
aluOps[VAdd] ← [op: add, cIn: zero, cOut: prev]; -- no trap
aluOps[VSub] ← [op: add, cIn: one, cOut: prev, invertB: TRUE];
aluOps[LAdd] ← [op: add, cIn: zero, cOut: zero]; -- IL
aluOps[LSub] ← [op: add, cIn: one, cOut: zero, invertB: TRUE];
aluOps[VAdd2] ← aluOps[VAdd];
aluOps[BndChk] ← [op: add, cIn: one, cOut: prev, invertB: TRUE];
aluOps[Or] ← [op: or, cIn: zero, cOut: prev];
aluOps[And] ← [op: and, cIn: zero, cOut: prev];
aluOps[Xor] ← [op: xor, cIn: zero, cOut: prev];
aluOps[FOP] ← aluOps[Or]; -- or anything else?
-- cBus, ifuIn, toPBus, fromPBus, ramA, ramB, kReg, left, right, field, aluOut, fuOut, r2B, r3A, st2A, st2B, st3A, pDriver, pIn
buses[left] ← NEW[BusRec ← [name: "left", trackPosX: 1, top: leftRow, bottom: fuRow]];
buses[right] ← NEW[BusRec ← [name: "right", trackPosX: 5, top: rightRow, bottom: aluRow]];
buses[st2A] ← NEW[BusRec ← [name: "st2A", trackPosX: 2, top: st2ARow, bottom: st2BRow]];
buses[st2B] ← NEW[BusRec ← [name: "st2B", trackPosX: 5, top: st2BRow, bottom: st3ARow]];
buses[st3A] ← NEW[BusRec ← [name: "st3A", trackPosX: 5, top: st3ARow, bottom: pDriverRow]];
buses[kReg] ← NEW[BusRec ← [name: "kReg", trackPosX: 3, top: kRegRow, bottom: ifuInRow]];
buses[field] ← NEW[BusRec ← [name: "field", trackPosX: 0, top: rightRow, bottom: fieldRow]];
buses[r2B] ← NEW[BusRec ← [name: "r2B", trackPosX: 3, top: rightRow, bottom: r3ARow]];
buses[r3A] ← NEW[BusRec ← [name: "r3A", trackPosX: 3, top: r3ARow, bottom: r3BRow]];
buses[cBus] ← NEW[BusRec ← [name: "cBus", trackPosX: 4, top: ramRow, bottom: dataInRow]];
buses[pDriver] ← NEW[BusRec ← [name: "pDriver", trackPosX: 5, top: pDriverRow, bottom: bottomRow]];
buses[ramA] ← NEW[BusRec ← [name: "ramA", trackPosX: 1, top: ramRow, bottom: leftRow]];
buses[ramB] ← NEW[BusRec ← [name: "ramB", trackPosX: 2, top: ramRow, bottom: st2ARow]];
buses[ifuIn] ← NEW[BusRec ← [name: "ifuIn", trackPosX: 5, top: kRegRow, bottom: rightRow]];
buses[aluOut] ← NEW[BusRec ← [name: "aluOut", trackPosX: 5, top: aluRow, bottom: r2BRow]];
buses[fuOut] ← NEW[BusRec ← [name: "fuOut", trackPosX: 5, top: r2BRow, bottom: fuRow]];
buses[pIn] ← NEW[BusRec ← [name: "pIn", trackPosX: 3, top: dataInRow, bottom: bottomRow]];
-- registers
sources[kRegRow] ←
NEW[SourceRec ← [name: "kReg",
position: 10,
nameSel: "selKRegSrc", -- PhB
sizeSel: 1,
output: kReg,
inputs: Array[ifuIn]]];
sources[rightRow] ←
NEW[SourceRec ← [name: "right",
position: 30,
nameSel: "selRightSrc", -- PhA
sizeSel: 5,
output: right,
inputs: Array[ramB, r2B, cBus, ifuIn, field]]];
sources[fieldRow] ←
NEW[SourceRec ← [name: "field",
position: 40,
nameSel: "selFieldSrc", -- PhA
sizeSel: 1,
output: field,
inputs: Array[cBus]]];
sources[leftRow] ←
NEW[SourceRec ← [name: "left",
position: 50,
nameSel: "selLeftSrc", -- PhA
sizeSel: 3,
output: left,
inputs: Array[ramA, r2B, cBus]]];
sources[st2ARow] ←
NEW[SourceRec ← [name: "st2A",
position: 60,
nameSel: "selSt2ASrc", -- PhA
sizeSel: 3,
output: st2A,
inputs: Array[ramB, r2B, cBus]]];
sources[r2BRow] ←
NEW[SourceRec ← [name: "r2B",
position: 80,
nameSel: "selRes2BASrc", -- PhB
sizeSel: 3,
output: r2B,
inputs: Array[aluOut, fuOut, left]]];
sources[st2BRow] ←
NEW[SourceRec ← [name: "st2B",
position: 100,
nameSel: "selSt2BASrc", -- PhB
sizeSel: 1,
output: st2B,
inputs: Array[st2A]]];
sources[st3ARow] ←
NEW[SourceRec ← [name: "st3A",
position: 110,
nameSel: "selSt3ABSrc", -- PhA
sizeSel: 2,
output: st3A,
inputs: Array[st2B, cBus]]];
sources[pDriverRow] ←
NEW[SourceRec ← [name: "pDriver",
-- special
position: 120,
output: pDriver,
inputs: Array[st3A, r2B]]];
sources[r3ARow] ←
NEW[SourceRec ← [name: "r3A",
position: 130,
nameSel: "selRes3ABSrc", -- PhA
sizeSel: 1,
output: r3A,
inputs: Array[r2B]]];
sources[r3BRow] ←
NEW[SourceRec ← [name: "r3B",
position: 140,
nameSel: "selRes3BASrc", -- PhB
tristate: TRUE,
sizeSel: 1,
output: cBus,
inputs: Array[r3A]]];
sources[dataInRow] ←
NEW[SourceRec ← [name: "dataIn",
position: 150,
nameSel: "selDataInSrc", -- PhB
tristate: TRUE,
sizeSel: 1,
output: cBus,
inputs: Array[pIn]]];
-- A table of the other rows in the datapath; positions are used by the register router
sources[ramRow] ← NEW[SourceRec ← [position: 0]];
sources[aluRow] ← NEW[SourceRec ← [position: 70]];
sources[fuRow] ← NEW[SourceRec ← [position: 90]];
sources[ifuInRow] ← NEW[SourceRec ← [position: 15]];
sources[bottomRow] ← NEW[SourceRec ← [position: 200]];
eu2Design ← PW.OpenDesign["EU"];
[] ← CDImports.Load[eu2Design, "Logic"];
eu2Cx ← Sisyph.Create[design: eu2Design];
alpsDesign ← BooleCore.cellLibrary;
alpsCx ← Sisyph.Create[alpsDesign];
END.